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may 14, 1999 (version 1.6) 6-5 6 xc4000e and xc4000x series features note: information in this data sheet covers the xc4000e, xc4000ex, and xc4000xl families. a separate data sheet covers the xc4000xla and xc4000xv families. electrical speci?cations and package/pin information are covered in separate sections for each family to make the information easier to access, review, and print. for access to these sec- tions, see the xilinx w eb linx web site at http://www .xilinx.com/par tinf o/databook.htm#xc4000 . ? system featured field-programmable gate arrays - select-ram tm memory: on-chip ultra-fast ram with - synchronous write option - dual-port ram option - fully pci compliant (speed grades -2 and faster) - abundant ?ip-?ops - flexible function generators - dedicated high-speed carry logic - wide edge decoders on each edge - hierarchy of interconnect lines - internal 3-state bus capability - eight global low-skew clock or signal distribution networks ? system performance beyond 80 mhz ? flexible array architecture ? low power segmented routing architecture ? systems-oriented features - ieee 1149.1-compatible boundary scan logic support - individually programmable output slew rate - programmable input pull-up or pull-down resistors - 12 ma sink current per xc4000e output ? con?gured by loading binary file - unlimited re-programmability ? read back capability - program veri?cation - internal node observability ? backward compatible with xc4000 devices ? development system runs on most common computer platforms - interfaces to popular design environments - fully automatic mapping, placement and routing - interactive design editor for design optimization low-voltage versions available ? low-voltage devices function at 3.0 - 3.6 volts ? xc4000xl: high performance low-voltage versions of xc4000ex devices additional xc4000x series features ? highest performance 3.3 v xc4000xl ? highest capacity over 180,000 usable gates ? 5 v tolerant i/os on xc4000xl ? 0.35 m m sram process for xc4000xl ? additional routing over xc4000e - almost twice the routing capacity for high-density designs ? buffered interconnect for maximum speed blocks ? improved versaring tm i/o interconnect for better fixed pinout flexibility ? 12 ma sink current per xc4000x output ? flexible new high-speed clock network - eight additional early buffers for shorter clock delays - virtually unlimited number of clock signals ? optional multiplexer or 2-input function generator on device outputs ? four additional address bits in master parallel con?guration mode ? xc4000xv family offers the highest density with 0.25 m m 2.5 v technology introduction xc4000 series high-performance, high-capacity field pro- grammable gate arrays (fpgas) provide the bene?ts of custom cmos vlsi, while avoiding the initial cost, long development cycle, and inherent risk of a conventional masked gate array. the result of thirteen years of fpga design experience and feedback from thousands of customers, these fpgas com- bine architectural versatility, on-chip select-ram memory with edge-triggered and dual-port modes, increased speed, abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs. the xc4000e and xc4000x series currently have 20 members, as shown in ta b l e 1 . 0 xc4000e and xc4000x series field programmable gate arrays may 14, 1999 (version 1.6) 00* product specification r
r xc4000e and xc4000x series field programmable gate arrays 6-6 may 14, 1999 (version 1.6) * max values of typical gate range include 20-30% of clbs used as ram. note: all functionality in low-voltage families is the same as in the corresponding 5-volt family, except where numerical references are made to timing or power. description xc4000 series devices are implemented with a regular, ?exible, programmable architecture of con?gurable logic blocks (clbs), interconnected by a powerful hierarchy of versatile routing resources, and surrounded by a perimeter of programmable input/output blocks (iobs). they have generous routing resources to accommodate the most complex interconnect patterns. the devices are customized by loading con?guration data into internal memory cells. the fpga can either actively read its con?guration data from an external serial or byte-parallel prom (master modes), or the con?guration data can be written into the fpga from an external device (slave and peripheral modes). xc4000 series fpgas are supported by powerful and sophisticated software, covering every aspect of design from schematic or behavioral entry, ?oor planning, simula- tion, automatic block placement and routing of intercon- nects, to the creation, downloading, and readback of the con?guration bit stream. because xilinx fpgas can be reprogrammed an unlimited number of times, they can be used in innovative designs where hardware is changed dynamically, or where hard- ware must be adapted to different user applications. fpgas are ideal for shortening design and development cycles, and also offer a cost-effective solution for produc- tion rates well beyond 5,000 systems per month. for lowest high-volume unit cost, a design can ?rst be implemented in the xc4000e or xc4000x, then migrated to one of xilinx compatible hardwire mask-programmed devices. taking advantage of re-con?guration fpga devices can be re-con?gured to change logic func- tion while resident in the system. this capability gives the system designer a new degree of freedom not available with any other type of logic. hardware can be changed as easily as software. design updates or modi?cations are easy, and can be made to products already in the ?eld. an fpga can even be re-con- ?gured dynamically to perform different functions at differ- ent times. re-con?gurable logic can be used to implement system self-diagnostics, create systems capable of being re-con- ?gured for different environments or operations, or imple- ment multi-purpose hardware for a given application. as an added bene?t, using re-con?gurable fpga devices simpli- ?es hardware design and debugging and shortens product time-to-market. table 1: xc4000e and xc4000x series field programmable gate arrays device logic cells max logic gates (no ram) max. ram bits (no logic) typical gate range (logic and ram)* clb matrix total clbs number of flip-flops max. user i/o xc4002xl 152 1,600 2,048 1,000 - 3,000 8 x 8 64 256 64 xc4003e 238 3,000 3,200 2,000 - 5,000 10 x 10 100 360 80 xc4005e/xl 466 5,000 6,272 3,000 - 9,000 14 x 14 196 616 112 xc4006e 608 6,000 8,192 4,000 - 12,000 16 x 16 256 768 128 xc4008e 770 8,000 10,368 6,000 - 15,000 18 x 18 324 936 144 xc4010e/xl 950 10,000 12,800 7,000 - 20,000 20 x 20 400 1,120 160 xc4013e/xl 1368 13,000 18,432 10,000 - 30,000 24 x 24 576 1,536 192 xc4020e/xl 1862 20,000 25,088 13,000 - 40,000 28 x 28 784 2,016 224 xc4025e 2432 25,000 32,768 15,000 - 45,000 32 x 32 1,024 2,560 256 xc4028ex/xl 2432 28,000 32,768 18,000 - 50,000 32 x 32 1,024 2,560 256 xc4036ex/xl 3078 36,000 41,472 22,000 - 65,000 36 x 36 1,296 3,168 288 xc4044xl 3800 44,000 51,200 27,000 - 80,000 40 x 40 1,600 3,840 320 xc4052xl 4598 52,000 61,952 33,000 - 100,000 44 x 44 1,936 4,576 352 xc4062xl 5472 62,000 73,728 40,000 - 130,000 48 x 48 2,304 5,376 384 xc4085xl 7448 85,000 100,352 55,000 - 180,000 56 x 56 3,136 7,168 448
r may 14, 1999 (version 1.6) 6-7 xc4000e and xc4000x series field programmable gate arrays 6 xc4000e and xc4000x series compared to the xc4000 for readers already familiar with the xc4000 family of xil- inx field programmable gate arrays, the major new fea- tures in the xc4000 series devices are listed in this section. the biggest advantages of xc4000e and xc4000x devices are signi?cantly increased system speed, greater capacity, and new architectural features, particularly select-ram memory. the xc4000x devices also offer many new routing features, including special high-speed clock buffers that can be used to capture input data with minimal delay. any xc4000e device is pinout- and bitstream-compatible with the corresponding xc4000 device. an existing xc4000 bitstream can be used to program an xc4000e device. however, since the xc4000e includes many new features, an xc4000e bitstream cannot be loaded into an xc4000 device. xc4000x series devices are not bitstream-compatible with equivalent array size devices in the xc4000 or xc4000e families. however, equivalent array size devices, such as the xc4025, xc4025e, xc4028ex, and xc4028xl, are pinout-compatible. improvements in xc4000e and xc4000x increased system speed xc4000e and xc4000x devices can run at synchronous system clock rates of up to 80 mhz, and internal perfor- mance can exceed 150 mhz. this increase in performance over the previous families stems from improvements in both device processing and system architecture. xc4000 series devices use a sub-micron multi-layer metal process. in addition, many architectural improvements have been made, as described below. the xc4000xl family is a high performance 3.3v family based on 0.35 m sram technology and supports system speeds to 80 mhz. pci compliance xc4000 series -2 and faster speed grades are fully pci compliant. xc4000e and xc4000x devices can be used to implement a one-chip pci solution. carry logic the speed of the carry logic chain has increased dramati- cally. some parameters, such as the delay on the carry chain through a single clb (t byp ), have improved by as much as 50% from xc4000 values. see fast carry logic on page 18 for more information. select-ram memory: edge-triggered, synchro- nous ram modes the ram in any clb can be con?gured for synchronous, edge-triggered, write operation. the read operation is not affected by this change to an edge-triggered write. dual-port ram a separate option converts the 16x2 ram in any clb into a 16x1 dual-port ram with simultaneous read/write. the function generators in each clb can be con?gured as either level-sensitive (asynchronous) single-port ram, edge-triggered (synchronous) single-port ram, edge-trig- gered (synchronous) dual-port ram, or as combinatorial logic. con?gurable ram content the ram content can now be loaded at con?guration time, so that the ram starts up with user-de?ned data. h function generator in current xc4000 series devices, the h function generator is more versatile than in the original xc4000. its inputs can come not only from the f and g function generators but also from up to three of the four control input lines. the h function generator can thus be totally or partially indepen- dent of the other two function generators, increasing the maximum capacity of the device. iob clock enable the two ?ip-?ops in each iob have a common clock enable input, which through con?guration can be activated individ- ually for the input or output ?ip-?op or both. this clock enable operates exactly like the ec pin on the xc4000 clb. this new feature makes the iobs more versatile, and avoids the need for clock gating. output drivers the output pull-up structure defaults to a ttl-like totem-pole. this driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below vcc, just like the xc4000 family outputs. alternatively, xc4000 series devices can be globally con?gured with cmos out- puts, with p-channel pull-up transistors pulling to vcc. also, the con?gurable pull-up resistor in the xc4000 series is a p-channel transistor that pulls to vcc, whereas in the origi- nal xc4000 family it is an n-channel transistor that pulls to a voltage one transistor threshold below vcc.
r xc4000e and xc4000x series field programmable gate arrays 6-8 may 14, 1999 (version 1.6) input thresholds the input thresholds of 5v devices can be globally con?g- ured for either ttl (1.2 v threshold) or cmos (2.5 v threshold), just like xc2000 and xc3000 inputs. the two global adjustments of input threshold and output level are independent of each other. the xc4000xl family has an input threshold of 1.6v, compatible with both 3.3v cmos and ttl levels. global signal access to logic there is additional access from global clocks to the f and g function generator inputs. con?guration pin pull-up resistors during configuration, these pins have weak pull-up resis- tors. for the most popular configuration mode, slave serial, the mode pins can thus be left unconnected. the three mode inputs can be individually configured with or without weak pull-up or pull-down resistors. a pull-down resistor value of 4.7 k w is recommended. the three mode inputs can be individually con?gured with or without weak pull-up or pull-down resistors after con?gu- ration. the pr ogram input pin has a permanent weak pull-up. soft start-up like the xc3000a, xc4000 series devices have soft start-up. when the con?guration process is ?nished and the device starts up, the ?rst activation of the outputs is automatically slew-rate limited. this feature avoids poten- tial ground bounce when all outputs are turned on simulta- neously. immediately after start-up, the slew rate of the individual outputs is, as in the xc4000 family, determined by the individual con?guration option. xc4000 and xc4000a compatibility existing xc4000 bitstreams can be used to con?gure an xc4000e device. xc4000a bitstreams must be recompiled for use with the xc4000e due to improved routing resources, although the devices are pin-for-pin compatible. additional improvements in xc4000x only increased routing new interconnect in the xc4000x includes twenty-two additional vertical lines in each column of clbs and twelve new horizontal lines in each row of clbs. the twelve quad lines in each clb row and column include optional repow- ering buffers for maximum speed. additional high-perfor- mance routing near the iobs enhances pin ?exibility. faster input and output a fast, dedicated early clock sourced by global clock buffers is available for the iobs. to ensure synchronization with the regular global clocks, a fast capture latch driven by the early clock is available. the input data can be initially loaded into the fast capture latch with the early clock, then transferred to the input ?ip-?op or latch with the low-skew global clock. a programmable delay on the input can be used to avoid hold-time requirements. see iob input sig- nals on page 20 for more information. latch capability in clbs storage elements in the xc4000x clb can be con?gured as either ?ip-?ops or latches. this capability makes the fpga highly synthesis-compatible. iob output mux from output clock a multiplexer in the iob allows the output clock to select either the output data or the iob clock enable as the output to the pad. thus, two different data signals can share a sin- gle output pad, effectively doubling the number of device outputs without requiring a larger, more expensive pack- age. this multiplexer can also be con?gured as an and-gate to implement a very fast pin-to-pin path. see iob output signals on page 23 for more information. additional address bits larger devices require more bits of con?guration data. a daisy chain of several large xc4000x devices may require a prom that cannot be addressed by the eighteen address bits supported in the xc4000e. the xc4000x series therefore extends the addressing in master parallel con?g- uration mode to 22 bits.
r may 14, 1999 (version 1.6) 6-9 xc4000e and xc4000x series field programmable gate arrays 6 detailed functional description xc4000 series devices achieve high speed through advanced semiconductor technology and improved archi- tecture. the xc4000e and xc4000x support system clock rates of up to 80 mhz and internal performance in excess of 150 mhz. compared to older xilinx fpga families, xc4000 series devices are more powerful. they offer on-chip edge-triggered and dual-port ram, clock enables on i/o ?ip-?ops, and wide-input decoders. they are more versatile in many applications, especially those involving ram. design cycles are faster due to a combination of increased routing resources and more sophisticated soft- ware. basic building blocks xilinx user-programmable gate arrays include two major con?gurable elements: con?gurable logic blocks (clbs) and input/output blocks (iobs). ? clbs provide the functional elements for constructing the users logic. ? iobs provide the interface between the package pins and internal signal lines. three other types of circuits are also available: ? 3-state buffers (tbufs) driving horizontal longlines are associated with each clb. ? wide edge decoders are available around the periphery of each device. ? an on-chip oscillator is provided. programmable interconnect resources provide routing paths to connect the inputs and outputs of these con?g- urable elements to the appropriate networks. the functionality of each circuit block is customized during con?guration by programming internal static memory cells. the values stored in these memory cells determine the logic functions and interconnections implemented in the fpga. each of these available circuits is described in this section. con?gurable logic blocks (clbs) con?gurable logic blocks implement most of the logic in an fpga. the principal clb elements are shown in figure 1 . two 4-input function generators (f and g) offer unrestricted versatility. most combinatorial logic functions need four or fewer inputs. however, a third function gener- ator (h) is provided. the h function generator has three inputs. either zero, one, or two of these inputs can be the outputs of f and g; the other input(s) are from outside the clb. the clb can, therefore, implement certain functions of up to nine variables, like parity check or expand- able-identity comparison of two sets of four inputs. each clb contains two storage elements that can be used to store the function generator outputs. however, the stor- age elements and function generators can also be used independently. these storage elements can be con?gured as ?ip-?ops in both xc4000e and xc4000x devices; in the xc4000x they can optionally be con?gured as latches. din can be used as a direct input to either of the two storage elements. h1 can drive the other through the h function generator. function generator outputs can also drive two outputs independent of the storage element outputs. this versatility increases logic capacity and simpli?es routing. thirteen clb inputs and four clb outputs provide access to the function generators and storage elements. these inputs and outputs connect to the programmable intercon- nect resources outside the block. function generators four independent inputs are provided to each of two func- tion generators (f1 - f4 and g1 - g4). these function gen- erators, with outputs labeled f and g, are each capable of implementing any arbitrarily de?ned boolean function of four inputs. the function generators are implemented as memory look-up tables. the propagation delay is therefore independent of the function implemented. a third function generator, labeled h, can implement any boolean function of its three inputs. two of these inputs can optionally be the f and g functional generator outputs. alternatively, one or both of these inputs can come from outside the clb (h2, h0). the third input must come from outside the block (h1). signals from the function generators can exit the clb on two outputs. f or h can be connected to the x output. g or h can be connected to the y output. a clb can be used to implement any of the following func- tions: ? any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variables 1 ? any single function of ?ve variables ? any function of four variables together with some functions of six variables ? some functions of up to nine variables. implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. the versatility of the clb function generators signi?cantly improves system speed. in addition, the design-software tools can deal with each function generator independently. this ?exibility improves cell usage. 1. when three separate functions are generated, one of the function outputs must be captured in a ?ip-?op internal to the clb. only two unregistered function generator outputs are available from the clb.
r xc4000e and xc4000x series field programmable gate arrays 6-10 may 14, 1999 (version 1.6) flip-flops the clb can pass the combinatorial output(s) to the inter- connect network, but can also store the combinatorial results or other incoming data in one or two ?ip-?ops, and connect their outputs to the interconnect network as well. the two edge-triggered d-type ?ip-?ops have common clock (k) and clock enable (ec) inputs. either or both clock inputs can also be permanently enabled. storage element functionality is described in ta bl e 2 . latches (xc4000x only) the clb storage elements can also be con?gured as latches. the two latches have common clock (k) and clock enable (ec) inputs. storage element functionality is described in ta bl e 2 . clock input each ?ip-?op can be triggered on either the rising or falling clock edge. the clock pin is shared by both storage ele- ments. however, the clock is individually invertible for each storage element. any inverter placed on the clock input is automatically absorbed into the clb. clock enable the clock enable signal (ec) is active high. the ec pin is shared by both storage elements. if left unconnected for either, the clock enable for that storage element defaults to the active state. ec is not invertible within the clb. logic function of g1-g4 g 4 g 3 g 2 g 1 g' logic function of f1-f4 f 4 f 3 f 2 f 1 f' logic function of f', g', and h1 h' din f' g' h' din f' g' h' g' h' h' f' s/r control d ec rd bypass bypass sd yq xq q s/r control d ec rd sd q 1 1 k (clock) multiplexer controlled by configuration program y x d in /h 2 h 1 sr/h 0 ec x6692 c 1 ???c 4 4 figure 1: simpli?ed block diagram of xc4000 series clb (ram and carry logic functions not shown) table 2: clb storage element functionality (active rising edge is shown) mode k ec sr d q power-up or gsr xxxxsr flip-flop xx1xsr __/ 1* 0* d d 0x0*xq latch 11*0*xq 01*0*dd both x 0 0* x q legend: x __/ sr 0* 1* dont care rising edge set or reset value. reset is default. input is low or unconnected (default value) input is high or unconnected (default value)
r may 14, 1999 (version 1.6) 6-11 xc4000e and xc4000x series field programmable gate arrays 6 set/reset an asynchronous storage element input (sr) can be con- ?gured as either set or reset. this con?guration option determines the state in which each ?ip-?op becomes oper- ational after con?guration. it also determines the effect of a global set/reset pulse during normal operation, and the effect of a pulse on the sr pin of the clb. all three set/reset functions for any single ?ip-?op are controlled by the same con?guration data bit. the set/reset state can be independently speci?ed for each ?ip-?op. this input can also be independently disabled for either ?ip-?op. the set/reset state is speci?ed by using the init attribute, or by placing the appropriate set or reset ?ip-?op library symbol. sr is active high. it is not invertible within the clb. global set/reset a separate global set/reset line (not shown in figure 1 ) sets or clears each storage element during power-up, re-con?guration, or when a dedicated reset net is driven active. this global net (gsr) does not compete with other routing resources; it uses a dedicated distribution network. each ?ip-?op is con?gured as either globally set or reset in the same way that the local set/reset (sr) is speci?ed. therefore, if a ?ip-?op is set by sr, it is also set by gsr. similarly, a reset ?ip-?op is reset by both sr and gsr. gsr can be driven from any user-programmable pin as a global reset input. to use this global net, place an input pad and input buffer in the schematic or hdl code, driving the gsr pin of the startup symbol. (see figure 2 .) a spe- ci?c pin location can be assigned to this input using a loc attribute or property, just as with any other user-program- mable pad. an inverter can optionally be inserted after the input buffer to invert the sense of the global set/reset sig- nal. alternatively, gsr can be driven from any internal node. data inputs and outputs the source of a storage element data input is programma- ble. it is driven by any of the functions f, g, and h, or by the direct in (din) block input. the ?ip-?ops or latches drive the xq and yq clb outputs. two fast feed-through paths are available, as shown in figure 1 . a two-to-one multiplexer on each of the xq and yq outputs selects between a storage element output and any of the control inputs. this bypass is sometimes used by the automated router to repower internal signals. control signals multiplexers in the clb map the four control inputs (c1 - c4 in figure 1 ) into the four internal control signals (h1, din/h2, sr/h0, and ec). any of these inputs can drive any of the four internal control signals. when the logic function is enabled, the four inputs are: ? ec enable clock ? sr/h0 asynchronous set/reset or h function generator input 0 ? din/h2 direct in or h function generator input 2 ? h1 h function generator input 1. when the memory function is enabled, the four inputs are: ? ec enable clock ? we write enable ? d0 data input to f and/or g function generator ? d1 data input to g function generator (16x1 and 16x2 modes) or 5th address bit (32x1 mode). using fpga flip-flops and latches the abundance of ?ip-?ops in the xc4000 series invites pipelined designs. this is a powerful way of increasing per- formance by breaking the function into smaller subfunc- tions and executing them in parallel, passing on the results through pipeline ?ip-?ops. this method should be seriously considered wherever throughput is more important than latency. to include a clb ?ip-?op, place the appropriate library symbol. for example, fdce is a d-type ?ip-?op with clock enable and asynchronous clear. the corresponding latch symbol (for the xc4000x only) is called ldce. in xc4000 series devices, the ?ip ?ops can be used as reg- isters or shift registers without blocking the function gener- ators from performing a different, perhaps unrelated task. this ability increases the functional capacity of the devices. the clb setup time is speci?ed between the function gen- erator inputs and the clock input k. therefore, the speci?ed clb ?ip-?op setup time includes the delay through the function generator. using function generators as ram optional modes for each clb make the memory look-up tables in the f and g function generators usable as an array of read/write memory cells. available modes are level-sensitive (similar to the xc4000/a/h families), edge-triggered, and dual-port edge-triggered. depending on the selected mode, a single clb can be con?gured as either a 16x2, 32x1, or 16x1 bit array. pad ibuf gsr gts clk donein q1q4 q2 q3 startup x5260 figure 2: schematic symbols for global set/reset
r xc4000e and xc4000x series field programmable gate arrays 6-12 may 14, 1999 (version 1.6) supported clb memory con?gurations and timing modes for single- and dual-port modes are shown in ta b l e 3 . xc4000 series devices are the ?rst programmable logic devices with edge-triggered (synchronous) and dual-port ram accessible to the user. edge-triggered ram simpli- ?es system timing. dual-port ram doubles the effective throughput of fifo applications. these features can be individually programmed in any xc4000 series clb. advantages of on-chip and edge-triggered ram the on-chip ram is extremely fast. the read access time is the same as the logic delay. the write access time is slightly slower. both access times are much faster than any off-chip solution, because they avoid i/o delays. edge-triggered ram, also called synchronous ram, is a feature never before available in a field programmable gate array. the simplicity of designing with edge-triggered ram, and the markedly higher achievable performance, add up to a signi?cant improvement over existing devices with on-chip ram. three application notes are available from xilinx that dis- cuss edge-triggered ram: xc4000e edge-triggered and dual-port ram capability, implementing fifos in xc4000e ram, and synchronous and asynchronous fifo designs . all three application notes apply to both xc4000e and xc4000x ram. ram con?guration options the function generators in any clb can be con?gured as ram arrays in the following sizes: ? two 16x1 rams: two data inputs and two data outputs with identical or, if preferred, different addressing for each ram ? one 32x1 ram: one data input and one data output. one f or g function generator can be con?gured as a 16x1 ram while the other function generators are used to imple- ment any function of up to 5 inputs. additionally, the xc4000 series ram may have either of two timing modes: ? edge-triggered (synchronous): data written by the designated edge of the clb clock. we acts as a true clock enable. ? level-sensitive (asynchronous): an external we signal acts as the write strobe. the selected timing mode applies to both function genera- tors within a clb when both are con?gured as ram. the number of read ports is also programmable: ? single port: each function generator has a common read and write port ? dual port: both function generators are con?gured together as a single 16x1 dual-port ram with one write port and two read ports. simultaneous read and write operations to the same or different addresses are supported. ram con?guration options are selected by placing the appropriate library symbol. choosing a ram con?guration mode the appropriate choice of ram mode for a given design should be based on timing and resource requirements, desired functionality, and the simplicity of the design pro- cess. recommended usage is shown in ta b l e 4 . the difference between level-sensitive, edge-triggered, and dual-port ram is only in the write operation. read operation and timing is identical for all modes of operation. ram inputs and outputs the f1-f4 and g1-g4 inputs to the function generators act as address lines, selecting a particular memory cell in each look-up table. the functionality of the clb control signals changes when the function generators are con?gured as ram. the din/h2, h1, and sr/h0 lines become the two data inputs (d0, d1) and the write enable (we) input for the 16x2 memory. when the 32x1 con?guration is selected, d1 acts as the ?fth address bit and d0 is the data input. the contents of the memory cell(s) being addressed are available at the f and g function-generator outputs. they can exit the clb through its x and y outputs, or can be cap- tured in the clb ?ip-?op(s). con?guring the clb function generators as read/write memory does not affect the functionality of the other por- table 3: supported ram modes 16 x 1 16 x 2 32 x 1 edge- triggered timing level- sensitive timing single-port ??? ? ? dual-port ? ? table 4: ram mode selection level-sens itive edge-trigg ered dual-port edge-trigg ered use for new designs? no yes yes size (16x1, registered) 1/2 clb 1/2 clb 1 clb simultaneous read/write no no yes relative performance x2x 2x (4x effective)
r may 14, 1999 (version 1.6) 6-13 xc4000e and xc4000x series field programmable gate arrays 6 tions of the clb, with the exception of the rede?nition of the control signals. in 16x2 and 16x1 modes, the h function generator can be used to implement boolean functions of f, g, and d1, and the d ?ip-?ops can latch the f, g, h, or d0 signals. single-port edge-triggered mode edge-triggered (synchronous) ram simpli?es timing requirements. xc4000 series edge-triggered ram timing operates like writing to a data register. data and address are presented. the register is enabled for writing by a logic high on the write enable input, we. then a rising or falling clock edge loads the data into the register, as shown in figure 3 . complex timing relationships between address, data, and write enable signals are not required, and the external write enable pulse becomes a simple clock enable. the active edge of wclk latches the address, input data, and we sig- nals. an internal write pulse is generated that performs the write. see figure 4 and figure 5 for block diagrams of a clb con?gured as 16x2 and 32x1 edge-triggered, sin- gle-port ram. the relationships between clb pins and ram inputs and outputs for single-port, edge-triggered mode are shown in ta b l e 5 . the write clock input (wclk) can be con?gured as active on either the rising edge (default) or the falling edge. it uses the same clb pin (k) used to clock the clb ?ip-?ops, but it can be independently inverted. consequently, the ram output can optionally be registered within the same clb either by the same clock edge as the ram, or by the oppo- site edge of this clock. the sense of wclk applies to both function generators in the clb when both are con?gured as ram. the we pin is active-high and is not invertible within the clb. note: the pulse following the active edge of wclk (t wps in figure 3 ) must be less than one millisecond wide. for most applications, this requirement is not overly restrictive; however, it must not be forgotten. stopping wclk at this point in the write cycle could result in excessive current and even damage to the larger devices if many clbs are con- ?gured as edge-triggered ram. x6461 wclk (k) we address data in data out old new t dss t dhs t ass t ahs t wss t wps t whs t wos t ilo t ilo figure 3: edge-triggered ram write timing table 5: single-port edge-triggered ram signals ram signal clb pin function d d0 or d1 (16x2, 16x1), d0 (32x1) data in a[3:0] f1-f4 or g1-g4 address a[4] d1 (32x1) address we we write enable wclk k clock spo (data out) f or g single port out (data out)
r xc4000e and xc4000x series field programmable gate arrays 6-14 may 14, 1999 (version 1.6) g' 4 g 1 ???g 4 f 1 ???f 4 c 1 ???c 4 write decoder 1 of 16 d in 16-latch array x6752 4 4 mux f' write decoder 1 of 16 d in 16-latch array read address read address write pulse latch enable latch enable k (clock) we d 1 d 0 ec write pulse mux 4 4 figure 4: 16x2 (or 16x1) edge-triggered single-port ram g' 4 g 1 ???g 4 f 1 ???f 4 c 1 ???c 4 write decoder 1 of 16 d in 16-latch array x6754 4 4 mux f' write decoder 1 of 16 d in 16-latch array read address read address write pulse latch enable latch enable k (clock) we d 1 /a 4 d 0 ec ec write pulse mux 4 4 h' figure 5: 32x1 edge-triggered single-port ram (f and g addresses are identical)
r may 14, 1999 (version 1.6) 6-15 xc4000e and xc4000x series field programmable gate arrays 6 dual-port edge-triggered mode in dual-port mode, both the f and g function generators are used to create a single 16x1 ram array with one write port and two read ports. the resulting ram array can be read and written simultaneously at two independent addresses. simultaneous read and write operations at the same address are also supported. dual-port mode always has edge-triggered write timing, as shown in figure 3 . figure 6 shows a simple model of an xc4000 series clb con?gured as dual-port ram. one address port, labeled a[3:0], supplies both the read and write address for the f function generator. this function generator behaves the same as a 16x1 single-port edge-triggered ram array. the ram output, single port out (spo), appears at the f func- tion generator output. spo, therefore, re?ects the data at address a[3:0]. the other address port, labeled dpra[3:0] for dual port read address, supplies the read address for the g function generator. the write address for the g function generator, however, comes from the address a[3:0]. the output from this 16x1 ram array, dual port out (dpo), appears at the g function generator output. dpo, therefore, re?ects the data at address dpra[3:0]. therefore, by using a[3:0] for the write address and dpra[3:0] for the read address, and reading only the dpo output, a fifo that can read and write simultaneously is easily generated. simultaneous access doubles the effec- tive throughput of the fifo. the relationships between clb pins and ram inputs and outputs for dual-port, edge-triggered mode are shown in ta b l e 6 . see figure 7 on page 16 for a block diagram of a clb con?gured in this mode. table 6: dual-port edge-triggered ram signals note: the pulse following the active edge of wclk (t wps in figure 3 ) must be less than one millisecond wide. for most applications, this requirement is not overly restrictive; however, it must not be forgotten. stopping wclk at this point in the write cycle could result in excessive current and even damage to the larger devices if many clbs are con- ?gured as edge-triggered ram. single-port level-sensitive timing mode note: edge-triggered mode is recommended for all new designs. level-sensitive mode, also called asynchronous mode, is still supported for xc4000 series backward-com- patibility with the xc4000 family. level-sensitive ram timing is simple in concept but can be complicated in execution. data and address signals are presented, then a positive pulse on the write enable pin (we) performs a write into the ram at the designated address. as indicated by the level-sensitive label, this ram acts like a latch. during the we high pulse, changing the data lines results in new data written to the old address. changing the address lines while we is high results in spu- rious data written to the new addressand possibly at other addresses as well, as the address lines inevitably do not all change simultaneously. the user must generate a carefully timed we signal. the delay on the we signal and the address lines must be care- fully veri?ed to ensure that we does not become active until after the address lines have settled, and that we goes inactive before the address lines change again. the data must be stable before and after the falling edge of we. in practical terms, we is usually generated by a 2x clock. if a 2x clock is not available, the falling edge of the system clock can be used. however, there are inherent risks in this approach, since the we pulse must be guaranteed inactive before the next rising edge of the system clock. several older application notes are available from xilinx that dis- cuss the design of level-sensitive rams. these application notes include xapp031, using the xc4000 ram capabil- ity , and xapp042, high-speed ram design in xc4000 . however, the edge-triggered ram available in the xc4000 series is superior to level-sensitive ram for almost every application. we we ddq dq d dpra[3:0] a[3:0] ar[3:0] aw[3:0] we d ar[3:0] aw[3:0] ram16x1d primitive f function generator g function generator dpo (dual port out) registered dpo spo (single port out) registered spo wclk x6755 figure 6: xc4000 series dual-port ram, simple model ram signal clb pin function d d0 data in a[3:0] f1-f4 read address for f, write address for f and g dpra[3:0] g1-g4 read address for g we we write enable wclk k clock spo f single port out (addressed by a[3:0]) dpo g dual port out (addressed by dpra[3:0])
r xc4000e and xc4000x series field programmable gate arrays 6-16 may 14, 1999 (version 1.6) figure 8 shows the write timing for level-sensitive, sin- gle-port ram. the relationships between clb pins and ram inputs and outputs for single-port level-sensitive mode are shown in ta b l e 7 . figure 9 and figure 10 show block diagrams of a clb con- ?gured as 16x2 and 32x1 level-sensitive, single-port ram. initializing ram at con?guration both ram and rom implementations of the xc4000 series devices are initialized during con?guration. the ini- tial contents are de?ned via an init attribute or property attached to the ram or rom symbol, as described in the schematic library guide. if not de?ned, all ram contents are initialized to all zeros, by default. ram initialization occurs only during con?guration. the ram content is not affected by global set/reset. table 7: single-port level-sensitive ram signals g' g 1 ???g 4 f 1 ???f 4 write decoder 1 of 16 d in 16-latch array x6748 4 4 mux f' write decoder 1 of 16 d in 16-latch array read address read address write pulse latch enable latch enable k (clock) write pulse mux 4 4 c 1 ???c 4 4 we d 1 d 0 ec figure 7: 16x1 edge-triggered dual-port ram ram signal clb pin function d d0 or d1 data in a[3:0] f1-f4 or g1-g4 address we we write enable o f or g data out wc t address write enable data in as t wp t ds t dh t required ah t x6462 figure 8: level-sensitive ram write timing
r may 14, 1999 (version 1.6) 6-17 xc4000e and xc4000x series field programmable gate arrays 6 enable g' 4 g 1 ???g 4 f 1 ???f 4 write decoder 1 of 16 d in 16-latch array x6746 4 read address mux enable f' write decoder 1 of 16 d in 16-latch array 4 read address mux 4 c 1 ???c 4 4 we d 1 d 0 ec figure 9: 16x2 (or 16x1) level-sensitive single-port ram enable write decoder 1 of 16 d in 16-latch array x6749 4 read address mux enable write decoder 1 of 16 d in 16-latch array 4 read address mux g' 4 g 1 ???g 4 f 1 ???f 4 c 1 ???c 4 4 f' we d 1 /a 4 d 0 ec 4 h' figure 10: 32x1 level-sensitive single-port ram (f and g addresses are identical)
r xc4000e and xc4000x series field programmable gate arrays 6-18 may 14, 1999 (version 1.6) fast carry logic each clb f and g function generator contains dedicated arithmetic logic for the fast generation of carry and borrow signals. this extra output is passed on to the function gen- erator in the adjacent clb. the carry chain is independent of normal routing resources. dedicated fast carry logic greatly increases the ef?ciency and performance of adders, subtractors, accumulators, comparators and counters. it also opens the door to many new applications involving arithmetic operation, where the previous generations of fpgas were not fast enough or too inef?cient. high-speed address offset calculations in micro- processor or graphics systems, and high-speed addition in digital signal processing are two typical applications. the two 4-input function generators can be con?gured as a 2-bit adder with built-in hidden carry that can be expanded to any length. this dedicated carry circuitry is so fast and ef?cient that conventional speed-up methods like carry generate/propagate are meaningless even at the 16-bit level, and of marginal bene?t at the 32-bit level. this fast carry logic is one of the more signi?cant features of the xc4000 series, speeding up arithmetic and counting into the 70 mhz range. the carry chain in xc4000e devices can run either up or down. at the top and bottom of the columns where there are no clbs above or below, the carry is propagated to the right. (see figure 11 .) in order to improve speed in the high-capacity xc4000x devices, which can potentially have very long carry chains, the carry chain travels upward only, as shown in figure 12 . additionally, standard intercon- nect can be used to route a carry signal in the downward direction. figure 13 on page 19 shows an xc4000e clb with dedi- cated fast carry logic. the carry logic in the xc4000x is similar, except that cout exits at the top only, and the sig- nal cindown does not exist. as shown in figure 13 , the carry logic shares operand and control inputs with the func- tion generators. the carry outputs connect to the function generators, where they are combined with the operands to form the sums. figure 14 on page 20 shows the details of the carry logic for the xc4000e. this diagram shows the contents of the box labeled carry logic in figure 13 . the xc4000x carry logic is very similar, but a multiplexer on the pass-through carry chain has been eliminated to reduce delay. additionally, in the xc4000x the multiplexer on the g4 path has a memory-programmable 0 input, which per- mits g4 to directly connect to cout. g4 thus becomes an additional high-speed initialization path for carry-in. the dedicated carry logic is discussed in detail in xilinx document xapp 013: using the dedicated carry logic in xc4000 . this discussion also applies to xc4000e devices, and to xc4000x devices when the minor logic changes are taken into account. the fast carry logic can be accessed by placing special library symbols, or by using xilinx relationally placed mac- ros (rpms) that already include these symbols. x6687 clb clb clb clb clb clb clb clb clb clb clb clb clb clb clb clb figure 11: available xc4000e carry propagation paths x6610 clb clb clb clb clb clb clb clb clb clb clb clb clb clb clb clb figure 12: available xc4000x carry propagation paths (dotted lines use general interconnect)
r may 14, 1999 (version 1.6) 6-19 xc4000e and xc4000x series field programmable gate arrays 6 dq s/r ec yq y din h g f g h dq s/r ec xq din h g f h x h f g g4 g3 g2 g1 f f3 f2 f1 f4 f carry g carry c c down carry logic d c c up k s/r ec h1 x6699 out in out in in c out0 figure 13: fast carry logic in xc4000e clb (shaded area not present in xc4000x)
r xc4000e and xc4000x series field programmable gate arrays 6-20 may 14, 1999 (version 1.6) input/output blocks (iobs) user-con?gurable input/output blocks (iobs) provide the interface between external package pins and the internal logic. each iob controls one package pin and can be con- ?gured for input, output, or bidirectional signals. figure 15 shows a simpli?ed block diagram of the xc4000e iob. a more complete diagram which includes the boundary scan logic of the xc4000e iob can be found in figure 40 on page 43 , in the boundary scan section. the xc4000x iob contains some special features not included in the xc4000e iob. these features are high- lighted in a simpli?ed block diagram found in figure 16 , and discussed throughout this section. when xc4000x special features are discussed, they are clearly identi?ed in the text. any feature not so identi?ed is present in both xc4000e and xc4000x devices. iob input signals two paths, labeled i1 and i2 in figure 15 and figure 16 , bring input signals into the array. inputs also connect to an input register that can be programmed as either an edge-triggered ?ip-?op or a level-sensitive latch. the choice is made by placing the appropriate library sym- bol. for example, ifd is the basic input ?ip-?op (rising edge triggered), and ild is the basic input latch (transpar- ent-high). variations with inverted clocks are available, and some combinations of latches and ?ip-?ops can be imple- mented in a single iob, as described in the xact libraries guide . the xc4000e inputs can be globally con?gured for either ttl (1.2v) or 5.0 volt cmos thresholds, using an option in the bitstream generation software. there is a slight input hysteresis of about 300mv. the xc4000e output levels are also con?gurable; the two global adjustments of input threshold and output level are independent. inputs on the xc4000xl are ttl compatible and 3.3v cmos compatible. outputs on the xc4000xl are pulled to the 3.3v positive supply. the inputs of xc4000 series 5-volt devices can be driven by the outputs of any 3.3-volt device, if the 5-volt inputs are in ttl mode. supported sources for xc4000 series device inputs are shown in ta bl e 8 . 01 01 m m 0 1 01 m 0 1 m 10 m m 0 3 m 1 m i g1 g4 f2 f1 f3 c out g2 g3 f4 c in up c in down x2000 to function generators m m m c out0 figure 14: detail of xc4000e dedicated carry logic
r may 14, 1999 (version 1.6) 6-21 xc4000e and xc4000x series field programmable gate arrays 6 q flip- flop/ latch d d ce ce q out t output clock i input clock clock enable delay pad flip-flop slew rate control output buffer input buffer passive pull-up/ pull-down 2 i 1 x6704 figure 15: simpli?ed block diagram of xc4000e iob q flip-flop/ latch fast capture latch d q latch d g d 0 1 ce ce q out t output clock i input clock clock enable pad flip-flop slew rate control output buffer output mux input buffer passive pull-up/ pull-down 2 i 1 x5984 delay delay figure 16: simpli?ed block diagram of xc4000x iob (shaded areas indicate differences from xc4000e)
r xc4000e and xc4000x series field programmable gate arrays 6-22 may 14, 1999 (version 1.6) xc4000xl 5-volt tolerant i/os the i/os on the xc4000xl are fully 5-volt tolerant even though the v cc is 3.3 volts. this allows 5 v signals to directly connect to the xc4000xl inputs without damage, as shown in ta b l e 8 . in addition, the 3.3 volt v cc can be applied before or after 5 volt signals are applied to the i/os. this makes the xc4000xl immune to power supply sequencing problems. registered inputs the i1 and i2 signals that exit the block can each carry either the direct or registered input signal. the input and output storage elements in each iob have a common clock enable input, which, through con?guration, can be activated individually for the input or output ?ip-?op, or both. this clock enable operates exactly like the ec pin on the xc4000 series clb. it cannot be inverted within the iob. the storage element behavior is shown in ta b l e 9 . table 9: input register functionality (active rising edge is shown) optional delay guarantees zero hold time the data input to the register can optionally be delayed by several nanoseconds. with the delay enabled, the setup time of the input ?ip-?op is increased so that normal clock routing does not result in a positive hold-time requirement. a positive hold time requirement can lead to unreliable, temperature- or processing-dependent operation. the input ?ip-?op setup time is de?ned between the data measured at the device i/o pin and the clock input at the iob (not at the clock pin). any routing delay from the device clock pin to the clock input of the iob must, therefore, be subtracted from this setup time to arrive at the real setup time requirement relative to the device pins. a short speci- ?ed setup time might, therefore, result in a negative setup time at the device pins, i.e., a positive hold-time require- ment. when a delay is inserted on the data line, more clock delay can be tolerated without causing a positive hold-time requirement. suf?cient delay eliminates the possibility of a data hold-time requirement at the external pin. the maxi- mum delay is therefore inserted as the default. the xc4000e iob has a one-tap delay element: either the delay is inserted (default), or it is not. the delay guarantees a zero hold time with respect to clocks routed through any of the xc4000e global clock buffers. (see global nets and buffers (xc4000e only) on page 35 for a description of the global clock buffers in the xc4000e.) for a shorter input register setup time, with non-zero hold, attach a nodelay attribute or property to the ?ip-?op. the xc4000x iob has a two-tap delay element, with choices of a full delay, a partial delay, or no delay. the attributes or properties used to select the desired delay are shown in ta b l e 1 0 . the choices are no added attribute, meddelay, and nodelay. the default setting, with no added attribute, ensures no hold time with respect to any of the xc4000x clock buffers, including the global low-skew buffers. meddelay ensures no hold time with respect to the global early buffers. inputs with nodelay may have a positive hold time with respect to all clock buffers. for a description of each of these buffers, see global nets and buffers (xc4000x only) on page 37 . table 10: xc4000x iob input delay element table 8: supported sources for xc4000 series device inputs source xc4000e/ex series inputs xc4000xl series inputs 5 v, ttl 5 v, cmos 3.3 v cmos any device, vcc = 3.3 v, cmos outputs ? unreli -able data ? xc4000 series, vcc = 5 v, ttl outputs ?? any device, vcc = 5 v, ttl outputs (voh 3.7 v) ?? any device, vcc = 5 v, cmos outputs ?? ? mode clock clock enable dq power-up or gsr xxxsr flip-flop __/ 1* d d 0xxq latch 1 1* x q 01*dd both x 0 x q legend: x __/ sr 0* 1* dont care rising edge set or reset value. reset is default. input is low or unconnected (default value) input is high or unconnected (default value) value when to use full delay (default, no attribute added) zero hold with respect to global low-skew buffer, global early buffer meddelay zero hold with respect to global early buffer nodelay short setup, positive hold time
r may 14, 1999 (version 1.6) 6-23 xc4000e and xc4000x series field programmable gate arrays 6 additional input latch for fast capture (xc4000x only) the xc4000x iob has an additional optional latch on the input. this latch, as shown in figure 16 , is clocked by the output clock the clock used for the output ?ip-?op rather than the input clock. therefore, two different clocks can be used to clock the two input storage elements. this additional latch allows the very fast capture of input data, which is then synchronized to the internal clock by the iob ?ip-?op or latch. to use this fast capture technique, drive the output clock pin (the fast capture latching signal) from the output of one of the global early buffers supplied in the xc4000x. the second storage element should be clocked by a global low-skew buffer, to synchronize the incoming data to the internal logic. (see figure 17 .) these special buffers are described in global nets and buffers (xc4000x only) on page 37 . the fast capture latch (fcl) is designed primarily for use with a global early buffer. for fast capture, a single clock signal is routed through both a global early buffer and a global low-skew buffer. (the two buffers share an input pad.) the fast capture latch is clocked by the global early buffer, and the standard iob ?ip-?op or latch is clocked by the global low-skew buffer. this mode is the safest way to use the fast capture latch, because the clock buffers on both storage elements are driven by the same pad. there is no external skew between clock pads to create potential problems. to place the fast capture latch in a design, use one of the special library symbols, ilffx or ilflx. ilffx is a trans- parent-low fast capture latch followed by an active-high input ?ip-?op. ilflx is a transparent-low fast capture latch followed by a transparent-high input latch. any of the clock inputs can be inverted before driving the library ele- ment, and the inverter is absorbed into the iob. if a single bufg output is used to drive both clock inputs, the soft- ware automatically runs the clock through both a global low-skew buffer and a global early buffer, and clocks the fast capture latch appropriately. figure 16 on page 21 also shows a two-tap delay on the input. by default, if the fast capture latch is used, the xilinx software assumes a global early buffer is driving the clock, and selects meddelay to ensure a zero hold time. select the desired delay based on the discussion in the previous subsection. iob output signals output signals can be optionally inverted within the iob, and can pass directly to the pad or be stored in an edge-triggered ?ip-?op. the functionality of this ?ip-?op is shown in ta bl e 1 1 . an active-high 3-state signal can be used to place the out- put buffer in a high-impedance state, implementing 3-state outputs or bidirectional i/o. under con?guration control, the output (out) and output 3-state (t) signals can be inverted. the polarity of these signals is independently con- ?gured for each iob. the 4-ma maximum output current speci?cation of many fpgas often forces the user to add external buffers, which are especially cumbersome on bidirectional i/o lines. the xc4000e and xc4000ex/xl devices solve many of these problems by providing a guaranteed output sink current of 12 ma. two adjacent outputs can be interconnected exter- nally to sink up to 24 ma. the xc4000e and xc4000ex/xl fpgas can thus directly drive buses on a printed circuit board. by default, the output pull-up structure is con?gured as a ttl-like totem-pole. the high driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below vcc. alternatively, the outputs can be globally con?g- ured as cmos drivers, with p-channel pull-up transistors pulling to vcc. this option, applied using the bitstream gen- eration software, applies to all outputs on the device. it is not individually programmable. in the xc4000xl, all out- puts are pulled to the positive supply rail. ipad ipad bufge bufgls c ce dq gf to internal logic ilffx x9013 figure 17: examples using xc4000x fcl table 11: output flip-flop functionality (active rising edge is shown) mode clock clock enable t d q power-up or gsr x x 0* x sr flip-flop x00*xq __/ 1* 0* d d xx1xz 0x0*xq legend: x __/ sr 0* 1* z dont care rising edge set or reset value. reset is default. input is low or unconnected (default value) input is high or unconnected (default value) 3-state
r xc4000e and xc4000x series field programmable gate arrays 6-24 may 14, 1999 (version 1.6) any xc4000 series 5-volt device with its outputs con?g- ured in ttl mode can drive the inputs of any typical 3.3-volt device. (for a detailed discussion of how to inter- face between 5 v and 3.3 v devices, see the 3v products section of the programmable logic data book .) supported destinations for xc4000 series device outputs are shown in ta b l e 1 2 . an output can be con?gured as open-drain (open-collector) by placing an obuft symbol in a schematic or hdl code, then tying the 3-state pin (t) to the output signal, and the input pin (i) to ground. (see figure 18 .) table 12: supported destinations for xc4000 series outputs output slew rate the slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti- cal signals. for critical signals, attach a fast attribute or property to the output buffer or ?ip-?op. for xc4000e devices, maximum total capacitive load for simultaneous fast mode switching in the same direction is 200 pf for all package pins between each power/ground pin pair. for xc4000x devices, additional internal power/ground pin pairs are connected to special power and ground planes within the packages, to reduce ground bounce. therefore, the maximum total capacitive load is 300 pf between each external power/ground pin pair. maximum loading may vary for the low-voltage devices. for slew-rate limited outputs this total is two times larger for each device type: 400 pf for xc4000e devices and 600 pf for xc4000x devices. this maximum capacitive load should not be exceeded, as it can result in ground bounce of greater than 1.5 v amplitude and more than 5 ns dura- tion. this level of ground bounce may cause undesired transient behavior on an output, or in the internal logic. this restriction is common to all high-speed digital ics, and is not particular to xilinx or the xc4000 series. xc4000 series devices have a feature called soft start-up, designed to reduce ground bounce when all out- puts are turned on simultaneously at the end of con?gura- tion. when the con?guration process is ?nished and the device starts up, the ?rst activation of the outputs is auto- matically slew-rate limited. immediately following the initial activation of the i/o, the slew rate of the individual outputs is determined by the individual con?guration option for each iob. global three-state a separate global 3-state line (not shown in figure 15 or figure 16 ) forces all fpga outputs to the high-impedance state, unless boundary scan is enabled and is executing an extest instruction. this global net (gts) does not com- pete with other routing resources; it uses a dedicated distri- bution network. gts can be driven from any user-programmable pin as a global 3-state input. to use this global net, place an input pad and input buffer in the schematic or hdl code, driving the gts pin of the startup symbol. a speci?c pin loca- tion can be assigned to this input using a loc attribute or property, just as with any other user-programmable pad. an inverter can optionally be inserted after the input buffer to invert the sense of the global 3-state signal. using gts is similar to gsr. see figure 2 on page 11 for details. alternatively, gts can be driven from any internal node. destination xc4000 series outputs 3.3 v, cmos 5 v, ttl 5 v, cmos any typical device, vcc = 3.3 v, cmos-threshold inputs ?? some 1 1. only if destination device has 5-v tolerant inputs any device, vcc = 5 v, ttl-threshold inputs ??? any device, vcc = 5 v, cmos-threshold inputs unreliable data ? x6702 opad obuft figure 18: open-drain output
r may 14, 1999 (version 1.6) 6-25 xc4000e and xc4000x series field programmable gate arrays 6 output multiplexer/2-input function generator (xc4000x only) as shown in figure 16 on page 21 , the output path in the xc4000x iob contains an additional multiplexer not avail- able in the xc4000e iob. the multiplexer can also be con- ?gured as a 2-input function generator, implementing a pass-gate, and-gate, or-gate, or xor-gate, with 0, 1, or 2 inverted inputs. the logic used to implement these func- tions is shown in the upper gray area of figure 16 . when con?gured as a multiplexer, this feature allows two output signals to time-share the same output pad; effec- tively doubling the number of device outputs without requir- ing a larger, more expensive package. when the mux is con?gured as a 2-input function genera- tor, logic can be implemented within the iob itself. com- bined with a global early buffer, this arrangement allows very high-speed gating of a single signal. for example, a wide decoder can be implemented in clbs, and its output gated with a read or write strobe driven by a bufge buffer, as shown in figure 19 . the critical-path pin-to-pin delay of this circuit is less than 6 nanoseconds. as shown in figure 16 , the iob input pins out, output clock, and clock enable have different delays and different ?exibilities regarding polarity. additionally, output clock sources are more limited than the other inputs. therefore, the xilinx software does not move logic into the iob func- tion generators unless explicitly directed to do so. the user can specify that the iob function generator be used, by placing special library symbols beginning with the letter o. for example, a 2-input and-gate in the iob func- tion generator is called oand2. use the symbol input pin labelled f for the signal on the critical path. this signal is placed on the ok pin the iob input with the shortest delay to the function generator. two examples are shown in figure 20 . other iob options there are a number of other programmable options in the xc4000 series iob. pull-up and pull-down resistors programmable pull-up and pull-down resistors are useful for tying unused pins to vcc or ground to minimize power consumption and reduce noise sensitivity. the con?gurable pull-up resistor is a p-channel transistor that pulls to vcc. the con?gurable pull-down resistor is an n-channel transis- tor that pulls to ground. the value of these resistors is 50 k w- 100 k w . this high value makes them unsuitable as wired-and pull-up resis- tors. the pull-up resistors for most user-programmable iobs are active during the con?guration process. see ta b l e 2 2 o n page 58 for a list of pins with pull-ups active before and dur- ing con?guration. after con?guration, voltage levels of unused pads, bonded or un-bonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. therefore, by default, unused pads are con?gured with the internal pull-up resis- tor active. alternatively, they can be individually con?gured with the pull-down resistor, or as a driven output, or to be driven by an external source. to activate the internal pull-up, attach the pullup library component to the net attached to the pad. to activate the internal pull-down, attach the pulldown library component to the net attached to the pad. independent clocks separate clock signals are provided for the input and output ?ip-?ops. the clock can be independently inverted for each ?ip-?op within the iob, generating either falling-edge or ris- ing-edge triggered ?ip-?ops. the clock inputs for each iob are independent, except that in the xc4000x, the fast capture latch shares an iob input with the output clock pin. early clock for iobs (xc4000x only) special early clocks are available for iobs. these clocks are sourced by the same sources as the global low-skew buffers, but are separately buffered. they have fewer loads and therefore less delay. the early clock can drive either the iob output clock or the iob input clock, or both. the early clock allows fast capture of input data, and fast clock-to-output on output data. the global early buffers that drive these clocks are described in global nets and buffers (xc4000x only) on page 37 . global set/reset as with the clb registers, the global set/reset signal (gsr) can be used to set or clear the input and output reg- isters, depending on the value of the init attribute or prop- erty. the two ?ip-?ops can be individually con?gured to set ipad f opad fast bufge oand2 from internal logic x9019 figure 19: fast pin-to-pin path in xc4000x oand2 f x6598 d0 s0 d1 o omux2 x6599 figure 20: and & mux symbols in xc4000x iob
r xc4000e and xc4000x series field programmable gate arrays 6-26 may 14, 1999 (version 1.6) or clear on reset and after con?guration. other than the glo- bal gsr net, no user-controlled set/reset signal is available to the i/o ?ip-?ops. the choice of set or clear applies to both the initial state of the ?ip-?op and the response to the global set/reset pulse. see global set/reset on page 11 for a description of how to use gsr. jtag support embedded logic attached to the iobs contains test struc- tures compatible with ieee standard 1149.1 for boundary scan testing, permitting easy chip and board-level testing. more information is provided in boundary scan on page 42 . three-state buffers a pair of 3-state buffers is associated with each clb in the array. (see figure 27 on page 30 .) these 3-state buffers can be used to drive signals onto the nearest horizontal longlines above and below the clb. they can therefore be used to implement multiplexed or bidirectional buses on the horizontal longlines, saving logic resources. programmable pull-up resistors attached to these longlines help to imple- ment a wide wired-and function. the buffer enable is an active-high 3-state (i.e. an active-low enable), as shown in ta b l e 1 3 . another 3-state buffer with similar access is located near each i/o block along the right and left edges of the array. (see figure 33 on page 34 .) the horizontal longlines driven by the 3-state buffers have a weak keeper at each end. this circuit prevents unde?ned ?oating levels. however, it is overridden by any driver, even a pull-up resistor. special longlines running along the perimeter of the array can be used to wire-and signals coming from nearby iobs or from internal longlines. these longlines form the wide edge decoders discussed in wide edge decoders on page 27 . three-state buffer modes the 3-state buffers can be con?gured in three modes: ? standard 3-state buffer ? wired-and with input on the i pin ? wired or-and standard 3-state buffer all three pins are used. place the library element buft. connect the input to the i pin and the output to the o pin. the t pin is an active-high 3-state (i.e. an active-low enable). tie the t pin to ground to implement a standard buffer. wired-and with input on the i pin the buffer can be used as a wired-and. use the wand1 library symbol, which is essentially an open-drain buffer. wand4, wand8, and wand16 are also available. see the xact libraries guide for further information. the t pin is internally tied to the i pin. connect the input to the i pin and the output to the o pin. connect the outputs of all the wand1s together and attach a pullup symbol. wired or-and the buffer can be con?gured as a wired or-and. a high level on either input turns off the output. use the wor2and library symbol, which is essentially an open-drain 2-input or gate. the two input pins are func- tionally equivalent. attach the two inputs to the i0 and i1 pins and tie the output to the o pin. tie the outputs of all the wor2ands together and attach a pullup symbol. three-state buffer examples figure 21 shows how to use the 3-state buffers to imple- ment a wired-and function. when all the buffer inputs are high, the pull-up resistor(s) provide the high output. figure 22 shows how to use the 3-state buffers to imple- ment a multiplexer. the selection is accomplished by the buffer 3-state signal. pay particular attention to the polarity of the t pin when using these buffers in a design. active-high 3-state (t) is identical to an active-low output enable, as shown in ta b l e 1 3 . table 13: three-state buffer functionality in t out x1z in 0 in p u l l u p z = d a l d b l (d c +d d ) l (d e +d f ) d e d f d c d d d b d a wand1 wand1 wor2and wor2and x6465 figure 21: open-drain buffers implement a wired-and function
r may 14, 1999 (version 1.6) 6-27 xc4000e and xc4000x series field programmable gate arrays 6 wide edge decoders dedicated decoder circuitry boosts the performance of wide decoding functions. when the address or data ?eld is wider than the function generator inputs, fpgas need multi-level decoding and are thus slower than pals. xc4000 series clbs have nine inputs. any decoder of up to nine inputs is, therefore, compact and fast. however, there is also a need for much wider decoders, especially for address decoding in large microprocessor systems. an xc4000 series fpga has four programmable decoders located on each edge of the device. the inputs to each decoder are any of the iob i1 signals on that edge plus one local interconnect per clb row or column. each row or col- umn of clbs provides up to three variables or their compli- ments., as shown in figure 23 . each decoder generates a high output (resistor pull-up) when the and condition of the selected inputs, or their complements, is true. this is analogous to a product term in typical pal devices. each of these wired-and gates is capable of accepting up to 42 inputs on the xc4005e and 72 on the xc4013e. there are up to 96 inputs for each decoder on the xc4028x and 132 on the xc4052x. the decoders may also be split in two when a larger number of narrower decoders are required, for a maximum of 32 decoders per device. the decoder outputs can drive clb inputs, so they can be combined with other logic to form a pal-like and/or struc- ture. the decoder outputs can also be routed directly to the chip outputs. for fastest speed, the output should be on the same chip edge as the decoder. very large pals can be emulated by oring the decoder outputs in a clb. this decoding feature covers what has long been considered a weakness of older fpgas. users often resorted to external pals for simple but fast decoding functions. now, the dedi- cated decoders in the xc4000 series device can imple- ment these functions fast and ef?ciently. to use the wide edge decoders, place one or more of the wand library symbols (wand1, wand4, wand8, wand16). attach a decode attribute or property to each wand symbol. tie the outputs together and attach a pul- lup symbol. location attributes or properties such as l (left edge) or tr (right half of top edge) should also be used to ensure the correct placement of the decoder inputs. on-chip oscillator xc4000 series devices include an internal oscillator. this oscillator is used to clock the power-on time-out, for con?g- uration memory clearing, and as the source of cclk in master con?guration modes. the oscillator runs at a nomi- nal 8 mhz frequency that varies with process, vcc, and temperature. the output frequency falls between 4 and 10 mhz. d n d c d b d a abcn z = d a ?a + d b ?b + d c ?c + d n ?n ~100 k w "weak keeper" x6466 buft buft buft buft figure 22: 3-state buffers implement a multiplexer iob iob b a interconnect ( c) ..... (a ?b ?c) ..... (a ?b ?c) ..... (a ?b ?c) ..... .i1 .i1 x2627 c figure 23: xc4000 series edge decoding example f16k f500k f8m f490 f15 x6703 osc4 figure 24: xc4000 series oscillator symbol
r xc4000e and xc4000x series field programmable gate arrays 6-28 may 14, 1999 (version 1.6) the oscillator output is optionally available after con?gura- tion. any two of four resynchronized taps of a built-in divider are also available. these taps are at the fourth, ninth, four- teenth and nineteenth bits of the divider. therefore, if the primary oscillator output is running at the nominal 8 mhz, the user has access to an 8 mhz clock, plus any two of 500 khz, 16khz, 490hz and 15hz (up to 10% lower for low-volt- age devices). these frequencies can vary by as much as -50% or +25%. these signals can be accessed by placing the osc4 library element in a schematic or in hdl code (see figure 24 ). the oscillator is automatically disabled after con?guration if the osc4 symbol is not used in the design. programmable interconnect all internal connections are composed of metal segments with programmable switching points and switching matrices to implement the desired routing. a structured, hierarchical matrix of routing resources is provided to achieve ef?cient automated routing. the xc4000e and xc4000x share a basic interconnect structure. xc4000x devices, however, have additional rout- ing not available in the xc4000e. the extra routing resources allow high utilization in high-capacity devices. all xc4000x-speci?c routing resources are clearly identi?ed throughout this section. any resources not identi?ed as xc4000x-speci?c are present in all xc4000 series devices. this section describes the varied routing resources avail- able in xc4000 series devices. the implementation soft- ware automatically assigns the appropriate resources based on the density and timing requirements of the design. interconnect overview there are several types of interconnect. ? clb routing is associated with each row and column of the clb array. ? iob routing forms a ring (called a versaring) around the outside of the clb array. it connects the i/o with the internal logic blocks. ? global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. global routing can also be used for other high-fanout signals. five interconnect types are distinguished by the relative length of their segments: single-length lines, double-length lines, quad and octal lines (xc4000x only), and longlines. in the xc4000x, direct connects allow fast data ?ow between adjacent clbs, and between iobs and clbs. extra routing is included in the iob pad ring. the xc4000x also includes a ring of octal interconnect lines near the iobs to improve pin-swapping and routing to locked pins. xc4000e/x devices include two types of global buffers. these global buffers have different properties, and are intended for different purposes. they are discussed in detail later in this section. clb routing connections a high-level diagram of the routing resources associated with one clb is shown in figure 25 . the shaded arrows represent routing present only in xc4000x devices. ta b l e 1 4 shows how much routing of each type is available in xc4000e and xc4000x clb arrays. clearly, very large designs, or designs with a great deal of interconnect, will route more easily in the xc4000x. smaller xc4000e designs, typically requiring signi?cantly less interconnect, do not require the additional routing. figure 27 on page 30 is a detailed diagram of both the xc4000e and the xc4000x clb, with associated routing. the shaded square is the programmable switch matrix, present in both the xc4000e and the xc4000x. the l-shaped shaded area is present only in xc4000x devices. as shown in the ?gure, the xc4000x block is essentially an xc4000e block with additional routing. clb inputs and outputs are distributed on all four sides, providing maximum routing ?exibility. in general, the entire architecture is symmetrical and regular. it is well suited to established placement and routing algorithms. inputs, out- puts, and function generators can freely swap positions within a clb to avoid routing congestion during the place- ment and routing operation.
r may 14, 1999 (version 1.6) 6-29 xc4000e and xc4000x series field programmable gate arrays 6 table 14: routing per clb in xc4000 series devices programmable switch matrices the horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (psm). each switch matrix consists of programmable pass transistors used to establish connections between the lines (see figure 26 ). for example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. similarly, a dou- ble-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix. single-length lines single-length lines provide the greatest interconnect ?exi- bility and offer fast routing between adjacent blocks. there are eight vertical and eight horizontal single-length lines associated with each clb. these lines connect the switch- ing matrices that are located in every row and a column of clbs. single-length lines are connected by way of the program- mable switch matrices, as shown in figure 28 . routing connectivity is shown in figure 27 . single-length lines incur a delay whenever they go through a switching matrix. therefore, they are not suitable for rout- ing signals for long distances. they are normally used to conduct signals within a localized area and to provide the branching for nets with fanout greater than one. x5994 quad quad single double long direct connect long clb long global clock long double single global clock carry chain direct connect figure 25: high-level routing diagram of xc4000 series clb (shaded arrows indicate xc4000x only) xc4000e xc4000x vertical horizontal vertical horizontal singles 8 8 8 8 doubles 4 4 4 4 quads 0 0 12 12 longlines 6 6 10 6 direct connects 002 2 globals 4 0 8 0 carry logic 2 0 1 0 total 24 18 45 32 six pass transistors per switch matrix interconnect point singles double double singles double double x6600 figure 26: programmable switch matrix (psm)
r xc4000e and xc4000x series field programmable gate arrays 6-30 may 14, 1999 (version 1.6) f1 c1 g1 f2 c2 g2 f3 c3 g3 f4 c4 g4 k x y xq yq long single double long global quad long single double long long double double quad global common to xc4000e and xc4000x xc4000x only programmable switch matrix clb direct feedback direct feedback figure 27: detail of programmable interconnect associated with xc4000 series clb
r may 14, 1999 (version 1.6) 6-31 xc4000e and xc4000x series field programmable gate arrays 6 double-length lines the double-length lines consist of a grid of metal segments, each twice as long as the single-length lines: they run past two clbs before entering a switch matrix. double-length lines are grouped in pairs with the switch matrices stag- gered, so that each line goes through a switch matrix at every other row or column of clbs (see figure 28 ). there are four vertical and four horizontal double-length lines associated with each clb. these lines provide faster signal routing over intermediate distances, while retaining routing ?exibility. double-length lines are connected by way of the programmable switch matrices. routing connectivity is shown in figure 27 . quad lines (xc4000x only) xc4000x devices also include twelve vertical and twelve horizontal quad lines per clb row and column. quad lines are four times as long as the single-length lines. they are interconnected via buffered switch matrices (shown as dia- monds in figure 27 on page 30 ). quad lines run past four clbs before entering a buffered switch matrix. they are grouped in fours, with the buffered switch matrices stag- gered, so that each line goes through a buffered switch matrix at every fourth clb location in that row or column. (see figure 29 .) the buffered switch matrixes have four pins, one on each edge. all of the pins are bidirectional. any pin can drive any or all of the other pins. each buffered switch matrix contains one buffer and six pass transistors. it resembles the programmable switch matrix shown in figure 26 , with the addition of a program- mable buffer. there can be up to two independent inputs and up to two independent outputs. only one of the inde- pendent inputs can be buffered. the place and route software automatically uses the timing requirements of the design to determine whether or not a quad line signal should be buffered. a heavily loaded signal is typically buffered, while a lightly loaded one is not. one scenario is to alternate buffers and pass transistors. this allows both vertical and horizontal quad lines to be buffered at alternating buffered switch matrices. due to the buffered switch matrices, quad lines are very fast. they provide the fastest available method of routing heavily loaded signals for long distances across the device. longlines longlines form a grid of metal interconnect segments that run the entire length or width of the array. longlines are intended for high fan-out, time-critical signal nets, or nets that are distributed over long distances. in xc4000x devices, quad lines are preferred for critical nets, because the buffered switch matrices make them faster for high fan-out nets. two horizontal longlines per clb can be driven by 3-state or open-drain drivers (tbufs). they can therefore imple- ment unidirectional or bidirectional buses, wide multiplex- ers, or wired-and functions. (see three-state buffers on page 26 for more details.) each horizontal longline driven by tbufs has either two (xc4000e) or eight (xc4000x) pull-up resistors. to acti- vate these resistors, attach a pullup symbol to the long-line net. the software automatically activates the appropriate number of pull-ups. there is also a weak keeper at each end of these two horizontal longlines. this clb psm psm psm psm clb clb clb clb clb clb clb clb doubles singles doubles x6601 figure 28: single- and double-length lines, with programmable switch matrices (psms) clb clb clb clb clb clb clb clb clb x9014 figure 29: quad lines (xc4000x only)
r xc4000e and xc4000x series field programmable gate arrays 6-32 may 14, 1999 (version 1.6) circuit prevents unde?ned ?oating levels. however, it is overridden by any driver, even a pull-up resistor. each xc4000e longline has a programmable splitter switch at its center, as does each xc4000x longline driven by tbufs. this switch can separate the line into two indepen- dent routing channels, each running half the width or height of the array. each xc4000x longline not driven by tbufs has a buff- ered programmable splitter switch at the 1/4, 1/2, and 3/4 points of the array. due to the buffering, xc4000x longline performance does not deteriorate with the larger array sizes. if the longline is split, the resulting partial longlines are independent. routing connectivity of the longlines is shown in figure 27 on page 30 . direct interconnect (xc4000x only) the xc4000x offers two direct, ef?cient and fast connec- tions between adjacent clbs. these nets facilitate a data ?ow from the left to the right side of the device, or from the top to the bottom, as shown in figure 30 . signals routed on the direct interconnect exhibit minimum interconnect prop- agation delay and use no general routing resources. the direct interconnect is also present between clbs and adjacent iobs. each iob on the left and top device edges has a direct path to the nearest clb. each clb on the right and bottom edges of the array has a direct path to the near- est two iobs, since there are two iobs for each row or col- umn of clbs. the place and route software uses direct interconnect whenever possible, to maximize routing resources and min- imize interconnect delays. i/o routing xc4000 series devices have additional routing around the iob ring. this routing is called a versaring. the versaring facilitates pin-swapping and redesign without affecting board layout. included are eight double-length lines span- ning two clbs (four iobs), and four longlines. global lines and wide edge decoder lines are provided. xc4000x devices also include eight octal lines. a high-level diagram of the versaring is shown in figure 31 . the shaded arrows represent routing present only in xc4000x devices. figure 33 on page 34 is a detailed diagram of the xc4000e and xc4000x versaring. the area shown includes two iobs. there are two iobs per clb row or column, there- fore this diagram corresponds to the clb routing diagram shown in figure 27 on page 30 . the shaded areas repre- sent routing and routing connections present only in xc4000x devices. octal i/o routing (xc4000x only) between the xc4000x clb array and the pad ring, eight interconnect tracks provide for versatility in pin assignment and ?xed pinout ?exibility. (see figure 32 on page 33 .) these routing tracks are called octals, because they can be broken every eight clbs (sixteen iobs) by a programma- ble buffer that also functions as a splitter switch. the buffers are staggered, so each line goes through a buffer at every eighth clb location around the device edge. the octal lines bend around the corners of the device. the lines cross at the corners in such a way that the segment most recently buffered before the turn has the farthest dis- tance to travel before the next buffer, as shown in figure 32 . clb iob x6603 iob iob iob iob iob iob iob iob iob iob iob iob iob iob iob iob iob iob iob clb clb clb clb clb ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ figure 30: xc4000x direct interconnect
r may 14, 1999 (version 1.6) 6-33 xc4000e and xc4000x series field programmable gate arrays 6 x5995 direct connect edge decode double long global clock octal quad single double long direct connect long interconnect iob wed wed wed iob figure 31: high-level routing diagram of xc4000 series versaring (left edge) wed = wide edge decoder, iob = i/o block (shaded arrows indicate xc4000x only) segment with nearest buffer connects to segment with furthest buffer iob iob iob iob x9015 figure 32: xc4000x octal i/o routing
r xc4000e and xc4000x series field programmable gate arrays 6-34 may 14, 1999 (version 1.6) t o c l b a r r a y ik ok i1 ce i2 decoder t o octal edge decode quad long single double long long double double global ik ok i1 ce i2 t o decoder decoder common to xc4000e and xc4000x xc4000x only iob iob direct figure 33: detail of programmable interconnect associated with xc4000 series iob (left edge)
r may 14, 1999 (version 1.6) 6-35 xc4000e and xc4000x series field programmable gate arrays 6 iob inputs and outputs interface with the octal lines via the single-length interconnect lines. single-length lines are also used for communication between the octals and dou- ble-length lines, quads, and longlines within the clb array. segmentation into buffered octals was found to be optimal for distributing signals over long distances around the device. global nets and buffers both the xc4000e and the xc4000x have dedicated glo- bal networks. these networks are designed to distribute clocks and other high fanout control signals throughout the devices with minimal skew. the global buffers are described in detail in the following sections. the text descriptions and diagrams are summarized in ta b l e 1 5 . the table shows which clb and iob clock pins can be sourced by which global buffers. in both xc4000e and xc4000x devices, placement of a library symbol called bufg results in the software choos- ing the appropriate clock buffer, based on the timing requirements of the design. the detailed information in these sections is included only for reference. global nets and buffers (xc4000e only) four vertical longlines in each clb column are driven exclusively by special global buffers. these longlines are in addition to the vertical longlines used for standard inter- connect. the four global lines can be driven by either of two types of global buffers. the clock pins of every clb and iob can also be sourced from local interconnect. two different types of clock buffers are available in the xc4000e: ? primary global buffers (bufgp) ? secondary global buffers (bufgs) four primary global buffers offer the shortest delay and negligible skew. four secondary global buffers have slightly longer delay and slightly more skew due to poten- tially heavier loading, but offer greater ?exibility when used to drive non-clock clb inputs. the primary global buffers must be driven by the semi-dedicated pads. the secondary global buffers can be sourced by either semi-dedicated pads or internal nets. each clb column has four dedicated vertical global lines. each of these lines can be accessed by one particular pri- mary global buffer, or by any of the secondary global buff- ers, as shown in figure 34 . each corner of the device has one primary buffer and one secondary buffer. iobs along the left and right edges have four vertical global longlines. top and bottom iobs can be clocked from the global lines in the adjacent clb column. a global buffer should be speci?ed for all timing-sensitive global signal distribution. to use a global buffer, place a bufgp (primary buffer), bufgs (secondary buffer), or bufg (either primary or secondary buffer) element in a schematic or in hdl code. if desired, attach a loc attribute or property to direct placement to the designated location. for example, attach a loc=l attribute or property to a bufgs symbol to direct that a buffer be placed in one of the two secondary global buffers on the left edge of the device, or a loc=bl to indicate the secondary global buffer on the bottom edge of the device, on the left. l = left, r = right, t = top, b = bottom table 15: clock pin access xc4000e xc4000x local inter- connect bufgp bufgs bufgls l & r bufge t & b bufge all clbs in quadrant ?????? all clbs in device ??? ? iobs on adjacent vertical half edge ?????? iobs on adjacent vertical full edge ???? ? iobs on adjacent horizontal half edge (direct) ? ? iobs on adjacent horizontal half edge (through clb globals) ?????? iobs on adjacent horizontal full edge (through clb globals) ??? ?
r xc4000e and xc4000x series field programmable gate arrays 6-36 may 14, 1999 (version 1.6) x4 x4 x6604 x4 4 one bufgp per global line one bufgp per global line any bufgs any bufgs bufgp pgck4 sgck4 pgck3 sgck3 bufgs bufgp bufgs iob iob iob iob iob iob iob iob iob iob iob bufgs bufgs bufgp bufgp sgck1 pgck1 sgck2 pgck2 iob x4 locals locals locals locals locals locals locals locals locals locals locals locals 4 4 4 clb clb locals locals clb clb locals locals figure 34: xc4000e global net distribution x4 4 iob clocks clb clocks (per column) clb clocks (per column) clb clocks (per column) clb clocks (per column) locals locals locals locals locals bufgls locals bufgls bufgls bufgls bufgls bufge bufge bufge bufge bufge bufge bufge bufge bufgls bufgls iob iob iob iob iob iob iob iob bufgls bufgls bufgls bufgls gck8 gck7 gck1 gck6 gck2 gck5 gck3 gck4 iob iob iob iob locals bufgls locals bufgls locals locals bufgls locals bufgls iob clocks iob clocks iob clocks 4 x8 x8 x4 x9018 8 8 8 8 8 bufgls locals 8 8 8 8 8 8 8 8 8 clb clb clb clb locals locals locals locals locals locals locals locals x8 x8 x8 x8 figure 35: xc4000x global net distribution
r may 14, 1999 (version 1.6) 6-37 xc4000e and xc4000x series field programmable gate arrays 6 global nets and buffers (xc4000x only) eight vertical longlines in each clb column are driven by special global buffers. these longlines are in addition to the vertical longlines used for standard interconnect. the glo- bal lines are broken in the center of the array, to allow faster distribution and to minimize skew across the whole array. each half-column global line has its own buffered multi- plexer, as shown in figure 35 . the top and bottom global lines cannot be connected across the center of the device, as this connection might introduce unacceptable skew. the top and bottom halves of the global lines must be sepa- rately driven although they can be driven by the same global buffer. the eight global lines in each clb column can be driven by either of two types of global buffers. they can also be driven by internal logic, because they can be accessed by single, double, and quad lines at the top, bottom, half, and quarter points. consequently, the number of different clocks that can be used simultaneously in an xc4000x device is very large. there are four global lines feeding the iobs at the left edge of the device. iobs along the right edge have eight global lines. there is a single global line along the top and bottom edges with access to the iobs. all iob global lines are bro- ken at the center. they cannot be connected across the center of the device, as this connection might introduce unacceptable skew. iob global lines can be driven from two types of global buff- ers, or from local interconnect. alternatively, top and bottom iobs can be clocked from the global lines in the adjacent clb column. two different types of clock buffers are available in the xc4000x: ? global low-skew buffers (bufgls) ? global early buffers (bufge) global low-skew buffers are the standard clock buffers. they should be used for most internal clocking, whenever a large portion of the device must be driven. global early buffers are designed to provide a faster clock access, but clb access is limited to one-fourth of the device. they also facilitate a faster i/o interface. figure 35 is a conceptual diagram of the global net struc- ture in the xc4000x. global early buffers and global low-skew buffers share a single pad. therefore, the same ipad symbol can drive one buffer of each type, in parallel. this con?guration is particu- larly useful when using the fast capture latches, as described in iob input signals on page 20 . paired global early and global low-skew buffers share a common input; they cannot be driven by two different signals. choosing an xc4000x clock buffer the clocking structure of the xc4000x provides a large variety of features. however, it can be simple to use, with- out understanding all the details. the software automati- cally handles clocks, along with all other routing, when the appropriate clock buffer is placed in the design. in fact, if a buffer symbol called bufg is placed, rather than a speci?c type of buffer, the software even chooses the buffer most appropriate for the design. the detailed information in this section is provided for those users who want a ?ner level of control over their designs. if ?ne control is desired, use the following summary and table 15 on page 35 to choose an appropriate clock buffer. ? the simplest thing to do is to use a global low-skew buffer. ? if a faster clock path is needed, try a bufg. the software will ?rst try to use a global low-skew buffer. if timing requirements are not met, a faster buffer will automatically be used. ? if a single quadrant of the chip is suf?cient for the clocked logic, and the timing requires a faster clock than the global low-skew buffer, use a global early buffer. global low-skew buffers each corner of the xc4000x device has two global low-skew buffers. any of the eight global low-skew buff- ers can drive any of the eight vertical global lines in a col- umn of clbs. in addition, any of the buffers can drive any of the four vertical lines accessing the iobs on the left edge of the device, and any of the eight vertical lines accessing the iobs on the right edge of the device. (see figure 36 on page 38 .) iobs at the top and bottom edges of the device are accessed through the vertical global lines in the clb array, as in the xc4000e. any global low-skew buffer can, therefore, access every iob and clb in the device. the global low-skew buffers can be driven by either semi-dedicated pads or internal logic. to use a global low-skew buffer, instantiate a bufgls element in a schematic or in hdl code. if desired, attach a loc attribute or property to direct placement to the desig- nated location. for example, attach a loc=t attribute or property to direct that a bufgls be placed in one of the two global low-skew buffers on the top edge of the device, or a loc=tr to indicate the global low-skew buffer on the top edge of the device, on the right.
r xc4000e and xc4000x series field programmable gate arrays 6-38 may 14, 1999 (version 1.6) global early buffers each corner of the xc4000x device has two global early buffers. the primary purpose of the global early buffers is to provide an earlier clock access than the potentially heavily-loaded global low-skew buffers. a clock source applied to both buffers will result in the global early clock edge occurring several nanoseconds earlier than the glo- bal low-skew buffer clock edge, due to the lighter loading. global early buffers also facilitate the fast capture of device inputs, using the fast capture latches described in iob input signals on page 20 . for fast capture, take a single clock signal, and route it through both a global early buffer and a global low-skew buffer. (the two buffers share an input pad.) use the global early buffer to clock the fast capture latch, and the global low-skew buffer to clock the normal input ?ip-?op or latch, as shown in figure 17 on page 23 . the global early buffers can also be used to provide a fast clock-to-out on device output pins. however, an early clock in the output ?ip-?op iob must be taken into consideration when calculating the internal clock speed for the design. the global early buffers at the left and right edges of the chip have slightly different capabilities than the ones at the top and bottom. refer to figure 37 , figure 38 , and figure 35 on page 36 while reading the following explana- tion. each global early buffer can access the eight vertical glo- bal lines for all clbs in the quadrant. therefore, only one-fourth of the clb clock pins can be accessed. this restriction is in large part responsible for the faster speed of the buffers, relative to the global low-skew buffers. the left-side global early buffers can each drive two of the four vertical lines accessing the iobs on the entire left edge of the device. the right-side global early buffers can each drive two of the eight vertical lines accessing the iobs on the entire right edge of the device. (see figure 37 .) each left and right global early buffer can also drive half of the iobs along either the top or bottom edge of the device, using a dedicated line that can only be accessed through the global early buffers. the top and bottom global early buffers can drive half of the iobs along either the left or right edge of the device, as shown in figure 38 . they can only access the top and bot- tom iobs via the clb global lines. 16 25 3 8 4 7 clb clb clb clb i o b i o b i o b i o b iob iob iob iob x6753 figure 36: any bufgls (gck1 - gck8) can drive any or all clock inputs on the device 16 25 3 8 4 7 clb clb clb clb i o b i o b i o b i o b iob iob iob iob x6751 figure 37: left and right bufges can drive any or all clock inputs in same quadrant or edge (gck1 is shown. gck2, gck5 and gck6 are similar.) 16 25 3 8 4 7 clb clb clb clb i o b i o b i o b i o b iob iob iob iob x6747 figure 38: top and bottom bufges can drive any or all clock inputs in same quadrant (gck8 is shown. gck3, gck4 and gck7 are similar.)
r may 14, 1999 (version 1.6) 6-39 xc4000e and xc4000x series field programmable gate arrays 6 the top and bottom global early buffers are about 1 ns slower clock to out than the left and right global early buff- ers. the global early buffers can be driven by either semi-ded- icated pads or internal logic. they share pads with the glo- bal low-skew buffers, so a single net can drive both global buffers, as described above. to use a global early buffer, place a bufge element in a schematic or in hdl code. if desired, attach a loc attribute or property to direct placement to the designated location. for example, attach a loc=t attribute or property to direct that a bufge be placed in one of the two global early buffers on the top edge of the device, or a loc=tr to indicate the global early buffer on the top edge of the device, on the right. power distribution power for the fpga is distributed through a grid to achieve high noise immunity and isolation between logic and i/o. inside the fpga, a dedicated vcc and ground ring sur- rounding the logic array provides power to the i/o drivers, as shown in figure 39 . an independent matrix of vcc and ground lines supplies the interior logic of the device. this power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately de-coupled. typically, a 0.1 m f capacitor connected between each vcc pin and the boards ground plane will provide adequate de-coupling. output buffers capable of driving/sinking the speci?ed 12 ma loads under speci?ed worst-case conditions may be capable of driving/sinking up to 10 times as much current under best case conditions. noise can be reduced by minimizing external load capaci- tance and reducing simultaneous output transitions in the same direction. it may also be bene?cial to locate heavily loaded output buffers near the ground pads. the i/o block output buffers have a slew-rate limited mode (default) which should be used where output rise and fall times are not speed-critical. pin descriptions there are three types of pins in the xc4000 series devices: ? permanently dedicated pins ? user i/o pins that can have special functions ? unrestricted user-programmable i/o pins. before and during con?guration, all outputs not used for the con?guration process are 3-stated with a 50 k w - 100 k w pull-up resistor. after con?guration, if an iob is unused it is con?gured as an input with a 50 k w - 100 k w pull-up resistor. xc4000 series devices have no dedicated reset input. any user i/o can be con?gured to drive the global set/reset net, gsr. see global set/reset on page 11 for more information on gsr. xc4000 series devices have no powerdown control input, as the xc3000 and xc2000 families do. the xc3000/xc2000 powerdown control also 3-stated all of the device i/o pins. for xc4000 series devices, use the global 3-state net, gts, instead. this net 3-states all outputs, but does not place the device in low-power mode. see iob output signals on page 23 for more information on gts. device pins for xc4000 series devices are described in ta b l e 1 6 . pin functions during con?guration for each of the seven con?guration modes are summarized in ta bl e 2 2 o n page 58 , in the con?guration timing section. gnd ground and vcc ring for i/o drivers vcc gnd vcc logic power grid x5422 figure 39: xc4000 series power distribution
r xc4000e and xc4000x series field programmable gate arrays 6-40 may 14, 1999 (version 1.6) table 16: pin descriptions pin name i/o during con?g. i/o after con?g. pin description permanently dedicated pins vcc i i eight or more (depending on package) connections to the nominal +5 v supply voltage (+3.3 v for low-voltage devices). all must be connected, and each must be decoupled with a 0.01 - 0.1 m f capacitor to ground. gnd i i eight or more (depending on package type) connections to ground. all must be con- nected. cclk i or o i during configuration, configuration clock (cclk) is an output in master modes or asyn- chronous peripheral mode, but is an input in slave mode and synchronous peripheral mode. after configuration, cclk has a weak pull-up resistor and can be selected as the readback clock. there is no cclk high or low time restriction on xc4000 series de- vices, except during readback. see violating the maximum high and low time spec- ification for the readback clock on page 56 for an explanation of this exception. done i/o o done is a bidirectional signal with an optional internal pull-up resistor. as an output, it indicates the completion of the configuration process. as an input, a low level on done can be configured to delay the global logic initialization and the enabling of outputs. the optional pull-up resistor is selected as an option in the xact step program that cre- ates the configuration bitstream. the resistor is included by default. program i i program is an active low input that forces the fpga to clear its configuration mem- ory. it is used to initiate a configuration cycle. when program goes high, the fpga finishes the current clear cycle and executes another complete clear cycle, before it goes into a wait state and releases init. the program pin has a permanent weak pull-up, so it need not be externally pulled up to vcc. user i/o pins that can have special functions rdy/ busy o i/o during peripheral mode configuration, this pin indicates when it is appropriate to write another byte of data into the fpga. the same status is also available on d7 in asyn- chronous peripheral mode, if a read operation is performed when the device is selected. after configuration, rdy/ busy is a user-programmable i/o pin. rdy/ busy is pulled high with a high-impedance pull-up prior to init going high. rclk o i/o during master parallel configuration, each change on the a0-a17 outputs (a0 - a21 for xc4000x) is preceded by a rising edge on rclk, a redundant output signal. rclk is useful for clocked proms. it is rarely used during configuration. after configuration, rclk is a user-programmable i/o pin. m0, m1, m2 i i (m0), o (m1), i (m2) as mode inputs, these pins are sampled after init goes high to determine the configu- ration mode to be used. after configuration, m0 and m2 can be used as inputs, and m1 can be used as a 3-state output. these three pins have no associated input or output registers. during configuration, these pins have weak pull-up resistors. for the most popular con- figuration mode, slave serial, the mode pins can thus be left unconnected. the three mode inputs can be individually configured with or without weak pull-up or pull-down re- sistors. a pull-down resistor value of 4.7 k w is recommended. these pins can only be used as inputs or outputs when called out by special schematic definitions. to use these pins, place the library components md0, md1, and md2 in- stead of the usual pad symbols. input or output buffers must still be used. tdo o o if boundary scan is used, this pin is the test data output. if boundary scan is not used, this pin is a 3-state output without a register, after configuration is completed. this pin can be user output only when called out by special schematic definitions. to use this pin, place the library component tdo instead of the usual pad symbol. an out- put buffer must still be used.
r may 14, 1999 (version 1.6) 6-41 xc4000e and xc4000x series field programmable gate arrays 6 tdi, tck, tms i i/o or i (jtag) if boundary scan is used, these pins are test data in, test clock, and test mode select inputs respectively. they come directly from the pads, bypassing the iobs. these pins can also be used as inputs to the clb logic after configuration is completed. if the bscan symbol is not placed in the design, all boundary scan functions are inhib- ited once configuration is completed, and these pins become user-programmable i/o. in this case, they must be called out by special schematic definitions. to use these pins, place the library components tdi, tck, and tms instead of the usual pad symbols. in- put or output buffers must still be used. hdc o i/o high during configuration (hdc) is driven high until the i/o go active. it is available as a control output indicating that configuration is not yet completed. after configuration, hdc is a user-programmable i/o pin. ldc o i/o low during configuration ( ldc) is driven low until the i/o go active. it is available as a control output indicating that configuration is not yet completed. after configuration, ldc is a user-programmable i/o pin. init i/o i/o before and during configuration, init is a bidirectional signal. a 1 k w - 10 k w external pull-up resistor is recommended. as an active-low open-drain output, init is held low during the power stabilization and internal clearing of the configuration memory. as an active-low input, it can be used to hold the fpga in the internal wait state before the start of configuration. master mode devices stay in a wait state an additional 30 to 300 m s after init has gone high. during configuration, a low on this output indicates that a configuration data error has occurred. after the i/o go active, init is a user-programmable i/o pin. pgck1 - pgck4 (xc4000e only) weak pull-up i or i/o four primary global inputs each drive a dedicated internal global net with short delay and minimal skew. if not used to drive a global buffer, any of these pins is a user-pro- grammable i/o. the pgck1-pgck4 pins drive the four primary global buffers. any input pad symbol connected directly to the input of a bufgp symbol is automatically placed on one of these pins. sgck1 - sgck4 (xc4000e only) weak pull-up i or i/o four secondary global inputs each drive a dedicated internal global net with short delay and minimal skew. these internal global nets can also be driven from internal logic. if not used to drive a global net, any of these pins is a user-programmable i/o pin. the sgck1-sgck4 pins provide the shortest path to the four secondary global buff- ers. any input pad symbol connected directly to the input of a bufgs symbol is auto- matically placed on one of these pins. gck1 - gck8 (xc4000x only) weak pull-up i or i/o eight inputs can each drive a global low-skew buffer. in addition, each can drive a glo- bal early buffer. each pair of global buffers can also be driven from internal logic, but must share an input signal. if not used to drive a global buffer, any of these pins is a user-programmable i/o. any input pad symbol connected directly to the input of a bufgls or bufge symbol is automatically placed on one of these pins. fclk1 - fclk4 (xc4000xla and xc4000xv only) weak pull-up i or i/o four inputs can each drive a fast clock (fclk) buffer which can deliver a clock signal to any iob clock input in the octant of the die served by the fast clock buffer. two fast clock buffers serve the two iob octants on the left side of the die and the other two fast clock buffers serve the two iob octants on the right side of the die. on each side of the die, one fast clock buffer serves the upper octant and the other serves the lower octant. if not used to drive a fast clock buffer, any of these pins is a user-programmable i/o. table 16: pin descriptions (continued) pin name i/o during con?g. i/o after con?g. pin description
r xc4000e and xc4000x series field programmable gate arrays 6-42 may 14, 1999 (version 1.6) boundary scan the bed of nails has been the traditional method of testing electronic assemblies. this approach has become less appropriate, due to closer pin spacing and more sophisti- cated assembly methods like surface-mount technology and multi-layer boards. the ieee boundary scan standard 1149.1 was developed to facilitate board-level testing of electronic assemblies. design and test engineers can imbed a standard test logic structure in their device to achieve high fault coverage for i/o and internal logic. this structure is easily implemented with a four-pin interface on any boundary scan-compatible ic. ieee 1149.1-compati- ble devices may be serial daisy-chained together, con- nected in parallel, or a combination of the two. the xc4000 series implements ieee 1149.1-compatible bypass, preload/sample and extest boundary scan instructions. when the boundary scan con?guration option is selected, three normal user i/o pins become ded- icated inputs for these functions. another user output pin becomes the dedicated boundary scan output. the details of how to enable this circuitry are covered later in this sec- tion. by exercising these input signals, the user can serially load commands and data into these devices to control the driv- ing of their outputs and to examine their inputs. this method is an improvement over bed-of-nails testing. it avoids the need to over-drive device outputs, and it reduces the user interface to four pins. an optional ?fth pin, a reset for the control logic, is described in the standard but is not implemented in xilinx devices. the dedicated on-chip logic implementing the ieee 1149.1 functions includes a 16-state machine, an instruction regis- ter and a number of data registers. the functional details can be found in the ieee 1149.1 speci?cation and are also discussed in the xilinx application note xapp 017: bound- ary scan in xc4000 devices . figure 40 on page 43 shows a simpli?ed block diagram of the xc4000e input/output block with boundary scan implemented. xc4000x boundary scan logic is identical. cs0, cs1, ws, rs i i/o these four inputs are used in asynchronous peripheral mode. the chip is selected when cs0 is low and cs1 is high. while the chip is selected, a low on write strobe ( ws) loads the data present on the d0 - d7 inputs into the internal data buffer. a low on read strobe ( rs) changes d7 into a status output high if ready, low if busy and drives d0 - d6 high. in express mode, cs1 is used as a serial-enable signal for daisy-chaining. ws and rs should be mutually exclusive, but if both are low simultaneously, the write strobe overrides. after configuration, these are user-programmable i/o pins. a0 - a17 o i/o during master parallel configuration, these 18 output pins address the configuration eprom. after configuration, they are user-programmable i/o pins. a18 - a21 (xc4003xl to xc4085xl) o i/o during master parallel configuration with an xc4000x master, these 4 output pins add 4 more bits to address the configuration eprom. after configuration, they are user-pro- grammable i/o pins. (see master parallel configuration section for additional details.) d0 - d7 i i/o during master parallel and peripheral configuration, these eight input pins receive con- figuration data. after configuration, they are user-programmable i/o pins. din i i/o during slave serial or master serial configuration, din is the serial configuration data input receiving data on the rising edge of cclk. during parallel configuration, din is the d0 input. after configuration, din is a user-programmable i/o pin. dout o i/o during configuration in any mode but express mode, dout is the serial configuration data output that can drive the din of daisy-chained slave fpgas. dout data changes on the falling edge of cclk, one-and-a-half cclk periods after it was received at the din input. in express modefor xc4000e and xc4000x only, dout is the status output that can drive the cs1 of daisy-chained fpgas, to enable and disable downstream devices. after configuration, dout is a user-programmable i/o pin. unrestricted user-programmable i/o pins i/o weak pull-up i/o these pins can be configured to be input and/or output after configuration is completed. before configuration is completed, these pins have an internal high-value pull-up resis- tor (25 k w - 100 k w ) that defines the logic level as high. table 16: pin descriptions (continued) pin name i/o during con?g. i/o after con?g. pin description
r may 14, 1999 (version 1.6) 6-43 xc4000e and xc4000x series field programmable gate arrays 6 figure 41 on page 44 is a diagram of the xc4000 series boundary scan logic. it includes three bits of data register per iob, the ieee 1149.1 test access port controller, and the instruction register with decodes. xc4000 series devices can also be con?gured through the boundary scan logic. see readback on page 55 . data registers the primary data register is the boundary scan register. for each iob pin in the fpga, bonded or not, it includes three bits for in, out and 3-state control. non-iob pins have appropriate partial bit population for in or out only. pr o- gram, cclk and done are not included in the boundary scan register. each extest capture-dr state captures all in, out, and 3-state pins. the data register also includes the following non-pin bits: tdo.t, and tdo.o, which are always bits 0 and 1 of the data register, respectively, and bscant.upd, which is always the last bit of the data register. these three bound- ary scan bits are special-purpose xilinx test signals. the other standard data register is the single ?ip-?op bypass register. it synchronizes data being passed through the fpga to the next downstream boundary scan device. the fpga provides two additional data registers that can be speci?ed using the bscan macro. the fpga provides two user pins (bscan.sel1 and bscan.sel2) which are the decodes of two user instructions. for these instructions, two corresponding pins (bscan.tdo1 and bscan.tdo2) allow user scan data to be shifted out on tdo. the data register clock (bscan.drck) is available for control of test logic which the user may wish to imple- ment with clbs. the nand of tck and run-test-idle is also provided (bscan.idle). figure 40: block diagram of xc4000e iob with boundary scan (some details not shown). xc4000x boundary scan logic is identical. d ec q m m q l rd m delay m m m m input clock ik i - capture i - update global s/r flip-flop/latch invert s/r input data 1 i1 input data 2 i2 x5792 pad v cc slew rate pull up m out sel d ec q rd m m m invert output m m invert s/r ouput clock ok clock enable ouput data o o - update q - capture o - capture boundary scan m extest ts - update ts - capture 3-state ts sd sd ts inv output ts/oe pull down input boundary scan boundary scan
r xc4000e and xc4000x series field programmable gate arrays 6-44 may 14, 1999 (version 1.6) instruction set the xc4000 series boundary scan instruction set also includes instructions to con?gure the device and read back the con?guration data. the instruction set is coded as shown in ta bl e 1 7 . bit sequence the bit sequence within each iob is: in, out, 3-state. the input-only m0 and m2 mode pins contribute only the in bit to the boundary scan i/o data register, while the out- put-only m1 pin contributes all three bits. the ?rst two bits in the i/o data register are tdo.t and tdo.o, which can be used for the capture of internal sig- nals. the ?nal bit is bscant.upd, which can be used to drive an internal net. these locations are primarily used by xilinx for internal testing. from a cavity-up view of the chip (as shown in xde or epic), starting in the upper right chip corner, the boundary scan data-register bits are ordered as shown in figure 42 . the device-speci?c pinout tables for the xc4000 series include the boundary scan locations for each iob pin. bsdl (boundary scan description language) ?les for xc4000 series devices are available on the xilinx ftp site. including boundary scan in a schematic if boundary scan is only to be used during con?guration, no special schematic elements need be included in the sche- matic or hdl code. in this case, the special boundary scan pins tdi, tms, tck and tdo can be used for user func- tions after con?guration. to indicate that boundary scan remain enabled after con?g- uration, place the bscan library symbol and connect the tdi, tms, tck and tdo pad symbols to the appropriate pins, as shown in figure 43 . even if the boundary scan symbol is used in a schematic, the input pins tms, tck, and tdi can still be used as inputs to be routed to internal logic. care must be taken not to force the chip into an undesired boundary scan state by inadvertently applying boundary scan input patterns to these pins. the simplest way to prevent this is to keep tms high, and then apply whatever signal is desired to tdi and tck. d q d q iob iob iob iob iob iob iob iob iob iob iob iob iob m u x bypass register iob iob tdo tdi iob iob iob 1 0 1 0 1 0 1 0 1 0 sd le dq d q d q 1 0 1 0 1 0 1 0 dq le sd sd le dq sd le dq iob d q 1 0 dq le sd iob.t data in iob.i iob.q iob.t iob.i shift/ capture clock data register dataout update extest x9016 instruction register figure 41: xc4000 series boundary scan logic
r may 14, 1999 (version 1.6) 6-45 xc4000e and xc4000x series field programmable gate arrays 6 table 17: boundary scan instructions avoiding inadvertent boundary scan if tms or tck is used as user i/o, care must be taken to ensure that at least one of these pins is held constant dur- ing con?guration. in some applications, a situation may occur where tms or tck is driven during con?guration. this may cause the device to go into boundary scan mode and disrupt the con?guration process. to prevent activation of boundary scan during con?gura- tion, do either of the following: ? tms: tie high to put the test access port controller in a benign reset state ? tck: tie high or lowdon't toggle this clock input. for more information regarding boundary scan, refer to the xilinx application note xapp 017.001, boundary scan in xc4000e devices . con?guration con?guration is the process of loading design-speci?c pro- gramming data into one or more fpgas to de?ne the func- tional operation of the internal blocks and their interconnections. this is somewhat like loading the com- mand registers of a programmable peripheral chip. xc4000 series devices use several hundred bits of con?guration data per clb and its associated interconnects. each con- ?guration bit de?nes the state of a static memory cell that controls either a function look-up table bit, a multiplexer input, or an interconnect pass transistor. the xact step development system translates the design into a netlist ?le. it automatically partitions, places and routes the logic and generates the con?guration data in prom format. special purpose pins three con?guration mode pins (m2, m1, m0) are sampled prior to con?guration to determine the con?guration mode. after con?guration, these pins can be used as auxiliary connections. m2 and m0 can be used as inputs, and m1 can be used as an output. the xact step development sys- tem does not use these resources unless they are explicitly speci?ed in the design entry. this is done by placing a spe- cial pad symbol called md2, md1, or md0 instead of the input or output pad symbol. in xc4000 series devices, the mode pins have weak pull-up resistors during con?guration. with all three mode pins high, slave serial mode is selected, which is the most popular con?guration mode. therefore, for the most com- mon con?guration mode, the mode pins can be left uncon- nected. (note, however, that the internal pull-up resistor value can be as high as 100 k w .) after con?guration, these pins can individually have weak pull-up or pull-down resis- tors, as speci?ed in the design. a pull-down resistor value of 4.7 k w is recommended. these pins are located in the lower left chip corner and are near the readback nets. this location allows convenient routing if compatibility with the xc2000 and xc3000 family conventions of m0/rt, m1/rd is desired. instruction i2 i1 i0 test selected tdo source i/o data source 0 0 0 extest dr dr 0 0 1 sample/pr eload dr pin/logic 0 1 0 user 1 bscan. tdo1 user logic 0 1 1 user 2 bscan. tdo2 user logic 1 0 0 readback readback data pin/logic 1 0 1 configure dout disabled 1 1 0 reserved 1 1 1 bypass bypass register bit 0 ( tdo end) bit 1 bit 2 tdo.t tdo.o top-edge iobs (right to left) left-edge iobs (top to bottom) md1.t md1.o md1.i md0.i md2.i bottom-edge iobs (left to right) right-edge iobs (bottom to top) b scant.upd (tdi end) x6075 figure 42: boundary scan bit sequence tdi tms tck tdo1 tdo2 tdo drck idle sel1 sel2 tdi tms tck tdo bscan to user logic ibuf optional from user logic to user logic x2675 figure 43: boundary scan schematic example
r xc4000e and xc4000x series field programmable gate arrays 6-46 may 14, 1999 (version 1.6) con?guration modes xc4000e devices have six con?guration modes. xc4000x devices have the same six modes, plus an additional con- ?guration mode. these modes are selected by a 3-bit input code applied to the m2, m1, and m0 inputs. there are three self-loading master modes, two peripheral modes, and a serial slave mode, which is used primarily for daisy-chained devices. the coding for mode selection is shown in ta bl e 1 8 . a detailed description of each con?guration mode, with tim- ing information, is included later in this data sheet. during con?guration, some of the i/o pins are used temporarily for the con?guration process. all pins used during con?gura- tion are shown in table 22 on page 58 . master modes the three master modes use an internal oscillator to gener- ate a con?guration clock (cclk) for driving potential slave devices. they also generate address and timing for exter- nal prom(s) containing the con?guration data. master parallel (up or down) modes generate the cclk signal and prom addresses and receive byte parallel data. the data is internally serialized into the fpga data-frame format. the up and down selection generates starting addresses at either zero or 3ffff (3fffff when 22 address lines are used), for compatibility with different microprocessor addressing conventions. the master serial mode generates cclk and receives the con?guration data in serial form from a xilinx serial-con?guration prom. cclk speed is selectable as either 1 mhz (default) or 8 mhz. con?guration always starts at the default slow fre- quency, then can switch to the higher frequency during the ?rst frame. frequency tolerance is -50% to +25%. additional address lines in xc4000 devices the xc4000x devices have additional address lines (a18-a21) allowing the additional address space required to daisy-chain several large devices. the extra address lines are programmable in xc4000ex devices. by default these address lines are not activated. in the default mode, the devices are compatible with existing xc4000 and xc4000e products. if desired, the extra address lines can be used by specifying the address lines option in bitgen as 22 (bitgen -g addresslines:22). the lines (a18-a21) are driven when a master device detects, via the bitstream, that it should be using all 22 address lines. because these pins will initially be pulled high by internal pull-ups, designers using master parallel up mode should use external pull down resistors on pins a18-a21. if master parallel down mode is used external resistors are not necessary. all 22 address lines are always active in master parallel modes with xc4000xl devices. the additional address lines behave identically to the lower order address lines. if the address lines option in bitgen is set to 18, it will be ignored by the xc4000xl device. the additional address lines (a18-a21) are not available in the pc84 package. peripheral modes the two peripheral modes accept byte-wide data from a bus. a rdy/ b usy status is available as a handshake sig- nal. in asynchronous peripheral mode, the internal oscilla- tor generates a cclk burst signal that serializes the byte-wide data. cclk can also drive slave devices. in the synchronous mode, an externally supplied clock input to cclk serializes the data. slave serial mode in slave serial mode, the fpga receives serial con?gura- tion data on the rising edge of cclk and, after loading its con?guration, passes additional data out, resynchronized on the next falling edge of cclk. multiple slave devices with identical con?gurations can be wired with parallel din inputs. in this way, multiple devices can be con?gured simultaneously. serial daisy chain multiple devices with different con?gurations can be con- nected together in a daisy chain, and a single combined bitstream used to con?gure the chain of slave devices. to con?gure a daisy chain of devices, wire the cclk pins of all devices in parallel, as shown in figure 51 on page 60 . connect the dout of each device to the din of the next. the lead or master fpga and following slaves each passes resynchronized con?guration data coming from a single source. the header data, including the length count, table 18: con?guration modes mode m2 m1 m0 cclk data master serial 0 0 0 output bit-serial slave serial 1 1 1 input bit-serial master parallel up 1 0 0 output byte-wide, increment from 00000 master parallel down 1 1 0 output byte-wide, decrement from 3ffff peripheral synchronous* 0 1 1 input byte-wide peripheral asynchronous 1 0 1 output byte-wide reserved 0 1 0 reserved 0 0 1 * can be considered byte-wide slave parallel
r may 14, 1999 (version 1.6) 6-47 xc4000e and xc4000x series field programmable gate arrays 6 is passed through and is captured by each fpga when it recognizes the 0010 preamble. following the length-count data, each fpga outputs a high on dout until it has received its required number of data frames. after an fpga has received its con?guration data, it passes on any additional frame start bits and con?guration data on dout. when the total number of con?guration clocks applied after memory initialization equals the value of the 24-bit length count, the fpgas begin the start-up sequence and become operational together. fpga i/o are normally released two cclk cycles after the last con?gura- tion bit is received. figure 47 on page 53 shows the start-up timing for an xc4000 series device. the daisy-chained bitstream is not simply a concatenation of the individual bitstreams. the prom ?le formatter must be used to combine the bitstreams for a daisy-chained con- ?guration. multi-family daisy chain all xilinx fpgas of the xc2000, xc3000, and xc4000 series use a compatible bitstream format and can, there- fore, be connected in a daisy chain in an arbitrary sequence. there is, however, one limitation. the lead device must belong to the highest family in the chain. if the chain contains xc4000 series devices, the master nor- mally cannot be an xc2000 or xc3000 device. the reason for this rule is shown in figure 47 on page 53 . since all devices in the chain store the same length count value and generate or receive one common sequence of cclk pulses, they all recognize length-count match on the same cclk edge, as indicated on the left edge of figure 47 . the master device then generates additional cclk pulses until it reaches its ?nish point f. the different families generate or require different numbers of additional cclk pulses until they reach f. not reaching f means that the device does not really ?nish its con?guration, although done may have gone high, the outputs became active, and the internal reset was released. for the xc4000 series device, not reaching f means that readback cannot be ini- tiated and most boundary scan instructions cannot be used. the user has some control over the relative timing of these events and can, therefore, make sure that they occur at the proper time and the ?nish point f is reached. timing is con- trolled using options in the bitstream generation software. xc3000 master with an xc4000 series slave some designers want to use an inexpensive lead device in peripheral mode and have the more precious i/o pins of the xc4000 series devices all available for user i/o. figure 44 provides a solution for that case. this solution requires one clb, one iob and pin, and an internal oscillator with a frequency of up to 5 mhz as a clock source. the xc3000 master device must be con?g- ured with late internal reset, which is the default option. one clb and one iob in the lead xc3000-family device are used to generate the additional cclk pulse required by the xc4000 series devices. when the lead device removes the internal reset signal, the 2-bit shift register responds to its clock input and generates an active low output signal for the duration of the subsequent clock period. an external connection between this output and cclk thus creates the extra cclk pulse. output connected to cclk oe/t 0 1 1 0 0 . . 0 0 1 1 1 . . reset x5223 etc active low output active high output figure 44: cclk generation for xc3000 master driving an xc4000 series slave
r xc4000e and xc4000x series field programmable gate arrays 6-48 may 14, 1999 (version 1.6) setting cclk frequency for master modes, cclk can be generated in either of two frequencies. in the default slow mode, the frequency ranges from 0.5 mhz to 1.25 mhz for xc4000e and xc4000ex devices and from 0.6 mhz to 1.8 mhz for xc4000xl devices. in fast cclk mode, the frequency ranges from 4 mhz to 10 mhz for xc4000ex devices and from 5 mhz to 15 mhz for xc4000xl devices. the fre- quency is selected by an option when running the bitstream generation software. if an xc4000 series master is driving an xc3000- or xc2000-family slave, slow cclk mode must be used. in addition, an xc4000xl device driving a xc4000e or xc4000ex should use slow mode. slow mode is the default. table 19: xc4000 series data stream formats data stream format the data stream (bitstream) format is identical for all con- ?guration modes. the data stream formats are shown in ta b l e 1 9 . bit-serial data is read from left to right, and byte-parallel data is effec- tively assembled from this serial bitstream, with the ?rst bit in each byte assigned to d0. the con?guration data stream begins with a string of eight ones, a preamble code, followed by a 24-bit length count and a separator ?eld of ones. this header is followed by the actual con?guration data in frames. the length and number of frames depends on the device type (see ta b l e 2 0 and ta b l e 2 1 ). each frame begins with a start ?eld and ends with an error check. a postamble code is required to signal the end of data for a single device. in all cases, additional start-up bytes of data are required to provide four clocks for the startup sequence at the end of con?guration. long daisy chains require additional startup bytes to shift the last data through the chain. all startup bytes are dont-cares; these bytes are not included in bitstreams created by the xilinx software. a selection of crc or non-crc error checking is allowed by the bitstream generation software. the non-crc error checking tests for a designated end-of-frame ?eld for each frame. for crc error checking, the software calculates a running crc and inserts a unique four-bit partial check at the end of each frame. the 11-bit crc check of the last frame of an fpga includes the last seven data bits. detection of an error results in the suspension of data load- ing and the pulling down of the init pin. in master modes, cclk and address signals continue to operate externally. the user must detect init and initialize a new con?guration by pulsing the pr ogram pin low or cycling vcc. data type all other modes (d0...) fill byte 11111111b preamble code 0010b length count count(23:0) fill bits 1111b start field 0b data frame data(n-1:0) crc or constant field check xxxx (crc) or 0110b extend write cycle postamble 01111111b start-up bytes xxh legend: not shaded once per bitstream light once per data frame dark once per device
r may 14, 1999 (version 1.6) 6-49 xc4000e and xc4000x series field programmable gate arrays 6 notes: 1. bits per frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits number of frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1 program data = (bits per frame x number of frames) + 8 postamble bits prom size = program data + 40 (header) + 8 2. the user can add more one bits as leading dummy bits in the header, or, if crc = off, as trailing dummy bits at the end of any frame, following the four error check bits. however, the length count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header. cyclic redundancy check (crc) for con?guration and readback the cyclic redundancy check is a method of error detec- tion in data transmission applications. generally, the trans- mitting system performs a calculation on the serial bitstream. the result of this calculation is tagged onto the data stream as additional check bits. the receiving system performs an identical calculation on the bitstream and com- pares the result with the received checksum. each data frame of the con?guration bitstream has four error bits at the end, as shown in ta b l e 1 9 . if a frame data error is detected during the loading of the fpga, the con- ?guration process with a potentially corrupted bitstream is terminated. the fpga pulls the init pin low and goes into a wait state. during readback, 11 bits of the 16-bit checksum are added to the end of the readback data stream. the checksum is computed using the crc-16 ccitt polynomial, as shown in figure 45 . the checksum consists of the 11 most signif- icant bits of the 16-bit code. a change in the checksum indi- cates a change in the readback bitstream. a comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. clb out- puts should not be included (read capture option not table 20: xc4000e program data device xc4003e xc4005e xc4006e xc4008e xc4010e xc4013e xc4020e xc4025e max logic gates 3,000 5,000 6,000 8,000 10,000 13,000 20,000 25,000 clbs (row x col.) 100 (10 x 10) 196 (14 x 14) 256 (16 x 16) 324 (18 x 18) 400 (20 x 20) 576 (24 x 24) 784 (28 x 28) 1,024 (32 x 32) iobs 80 112 128 144 160 192 224 256 flip-flops 360 616 768 936 1,120 1,536 2,016 2,560 bits per frame 126 166 186 206 226 266 306 346 frames 428 572 644 716 788 932 1,076 1,220 program data 53,936 94,960 119,792 147,504 178,096 247,920 329,264 422,128 prom size (bits) 53,984 95,008 119,840 147,552 178,144 247,968 329,312 422,176 table 21: xc4000ex/xl program data device xc4002xl xc4005 xc4010 xc4013 xc4020 xc4028 xc4036 xc4044 xc4052 xc4062 xc4085 max logic gates 2,000 5,000 10,000 13,000 20,000 28,000 36,000 44,000 52,000 62,000 85,000 clbs (row x column) 64 (8 x 8) 196 (14 x 14) 400 (20 x 20) 576 (24 x 24) 784 (28 x 28) 1,024 (32 x 32) 1,296 (36 x 36) 1,600 (40 x 40) 1,936 (44 x 44) 2,304 (48 x 48) 3,136 (56 x 56) iobs 64 112 160 192 224 256 288 320 352 384 448 flip-flops 256 616 1,120 1,536 2,016 2,560 3,168 3,840 4,576 5,376 7,168 bits per frame 133 205 277 325 373 421 469 517 565 613 709 frames 459 741 1,023 1,211 1,399 1,587 1,775 1,963 2,151 2,339 2,715 program data 61,052 151,910 283,376 393,580 521,832 668,124 832,480 1,014,876 1,215,320 1,433,804 1,924,940 prom size (bits) 61,104 151,960 283,424 393,632 521,880 668,172 832,528 1,014,924 1,215,368 1,433,852 1,924,992 notes: 1. bits per frame = (13 x number of rows) + 9 for the top + 17 for the bottom + 8 + 1 start bit + 4 error check bits. frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4. program data = (bits per frame x number of frames) + 5 postamble bits. prom size = (program data + 40 header bits + 8 start bits) rounded up to the nearest byte. 2. the user can add more one bits as leading dummy bits in the header, or, if crc = off, as trailing dummy bits at the end of any frame, following the four error check bits. however, the length count value must be adjusted for all such extra one bits, even for extra leading ones at the beginning of the header.
r xc4000e and xc4000x series field programmable gate arrays 6-50 may 14, 1999 (version 1.6) used), and if ram is present, the ram content must be unchanged. statistically, one error out of 2048 might go undetected. con?guration sequence there are four major steps in the xc4000 series power-up con?guration sequence. ? con?guration memory clear ? initialization ? con?guration ? start-up the full process is illustrated in figure 46 . con?guration memory clear when power is ?rst applied or is reapplied to an fpga, an internal circuit forces initialization of the con?guration logic. when vcc reaches an operational level, and the circuit passes the write and read test of a sample pair of con?gu- ration bits, a time delay is started. this time delay is nomi- nally 16 ms, and up to 10% longer in the low-voltage devices. the delay is four times as long when in master modes (m0 low), to allow ample time for all slaves to reach a stable vcc. when all init pins are tied together, as rec- ommended, the longest delay takes precedence. there- fore, devices with different time delays can easily be mixed and matched in a daisy chain. this delay is applied only on power-up. it is not applied when re-con?guring an fpga by pulsing the pr ogram pin 0 x2 2 3456789101112 13 14 1 x15 x16 15 serial data in 1 0 151413121110 9 8 7 65 1 1 1 1 crc ?checksum last data frame start bit x1789 polynomial: x16 + x15 + x2 + 1 readback data stream figure 45: circuit for generating crc-16 init high? if master sample mode lines load one configuration data frame frame error pass configuration data to dout v cc >3.5 v no yes yes no no yes operational start-up sequence no yes ~1.3 m s per frame master waits 50 to 250 s before sampling mode lines master cclk goes active f pull init low and stop x6076 extest* sample/preload bypass configure* (* if program = high) sample/preload bypass extest sample preload bypass user 1 user 2 configure readback if boundary scan is selected config- uration memory full cclk count equals length count completely clear configuration memory once more ldc output = l, hdc output = h boundary scan instructions available: i/o active keep clearing configuration memory test m0 generate one time-out pulse of 16 or 64 ms program = low no yes yes figure 46: power-up con?guration sequence
r may 14, 1999 (version 1.6) 6-51 xc4000e and xc4000x series field programmable gate arrays 6 low. during this time delay, or as long as the pr ogram input is asserted, the con?guration logic is held in a con?g- uration memory clear state. the con?guration-memory frames are consecutively initialized, using the internal oscil- lator. at the end of each complete pass through the frame addressing, the power-on time-out delay circuitry and the level of the pr ogram pin are tested. if neither is asserted, the logic initiates one additional clearing of the con?gura- tion frames and then tests the init input. initialization during initialization and con?guration, user pins hdc, ldc, init and done provide status outputs for the system inter- face. the outputs ldc, init and done are held low and hdc is held high starting at the initial application of power. the open drain init pin is released after the ?nal initializa- tion pass through the frame addresses. there is a deliber- ate delay of 50 to 250 m s (up to 10% longer for low-voltage devices) before a master-mode device recognizes an inac- tive init. two internal clocks after the init pin is recognized as high, the fpga samples the three mode lines to deter- mine the con?guration mode. the appropriate interface lines become active and the con?guration preamble and data can be loaded.con?guration the 0010 preamble code indicates that the following 24 bits represent the length count. the length count is the total number of con?guration clocks needed to load the com- plete con?guration data. (four additional con?guration clocks are required to complete the con?guration process, as discussed below.) after the preamble and the length count have been passed through to all devices in the daisy chain, dout is held high to prevent frame start bits from reaching any daisy-chained devices. a speci?c con?guration bit, early in the ?rst frame of a mas- ter device, controls the con?guration-clock rate and can increase it by a factor of eight. therefore, if a fast con?gu- ration clock is selected by the bitstream, the slower clock rate is used until this con?guration bit is detected. each frame has a start ?eld followed by the frame-con?gu- ration data bits and a frame error ?eld. if a frame data error is detected, the fpga halts loading, and signals the error by pulling the open-drain init pin low. after all con?gura- tion frames have been loaded into an fpga, dout again follows the input data so that the remaining data is passed on to the next device. delaying con?guration after power-up there are two methods of delaying con?guration after power-up: put a logic low on the pr ogram input, or pull the bidirectional init pin low, using an open-collector (open-drain) driver. (see figure 46 on page 50 .) a low on the pr ogram input is the more radical approach, and is recommended when the power-supply rise time is excessive or poorly de?ned. as long as pr o- gram is low, the fpga keeps clearing its con?guration memory. when pr ogram goes high, the con?guration memory is cleared one more time, followed by the begin- ning of con?guration, provided the init input is not exter- nally held low. note that a low on the pr ogram input automatically forces a low on the init output. the xc4000 series pr ogram pin has a permanent weak pull-up. using an open-collector or open-drain driver to hold init low before the beginning of con?guration causes the fpga to wait after completing the con?guration memory clear operation. when init is no longer held low exter- nally, the device determines its con?guration mode by cap- turing its mode pins, and is ready to start the con?guration process. a master device waits up to an additional 250 m s to make sure that any slaves in the optional daisy chain have seen that init is high. start-up start-up is the transition from the con?guration process to the intended user operation. this transition involves a change from one clock source to another, and a change from interfacing parallel or serial con?guration data where most outputs are 3-stated, to normal operation with i/o pins active in the user-system. start-up must make sure that the user-logic wakes up gracefully, that the outputs become active without causing contention with the con?guration sig- nals, and that the internal ?ip-?ops are released from the global reset or set at the right time. figure 47 describes start-up timing for the three xilinx fam- ilies in detail. the con?guration modes can use any of the four timing sequences. to access the internal start-up signals, place the startup library symbol. start-up timing different fpga families have different start-up sequences. the xc2000 family goes through a ?xed sequence. done goes high and the internal global reset is de-activated one cclk period after the i/o become active. the xc3000a family offers some ?exibility. done can be programmed to go high one cclk period before or after the i/o become active. independent of done, the internal global reset is de-activated one cclk period before or after the i/o become active. the xc4000 series offers additional ?exibility. the three events done going high, the internal set/reset being de-activated, and the user i/o going active can all occur in any arbitrary sequence. each of them can occur one cclk period before or after, or simultaneous with, any of the others. this relative timing is selected by means of soft- ware options in the bitstream generation software.
r xc4000e and xc4000x series field programmable gate arrays 6-52 may 14, 1999 (version 1.6) the default option, and the most practical one, is for done to go high ?rst, disconnecting the con?guration data source and avoiding any contention when the i/os become active one clock later. reset/set is then released another clock period later to make sure that user-operation starts from stable internal conditions. this is the most common sequence, shown with heavy lines in figure 47 , but the designer can modify it to meet particular requirements. normally, the start-up sequence is controlled by the internal device oscillator output (cclk), which is asynchronous to the system clock. xc4000 series offers another start-up clocking option, uclk_nosync. the three events described above need not be triggered by cclk. they can, as a con?guration option, be triggered by a user clock. this means that the device can wake up in synchronism with the user system. when the uclk_sync option is enabled, the user can externally hold the open-drain done output low, and thus stall all further progress in the start-up sequence until done is released and has gone high. this option can be used to force synchronization of several fpgas to a com- mon user clock, or to guarantee that all devices are suc- cessfully con?gured before any i/os go active. if either of these two options is selected, and no user clock is speci?ed in the design or attached to the device, the chip could reach a point where the con?guration of the device is complete and the done pin is asserted, but the outputs do not become active. the solution is either to recreate the bit- stream specifying the start-up clock as cclk, or to supply the appropriate user clock. start-up sequence the start-up sequence begins when the con?guration memory is full, and the total number of con?guration clocks received since init went high equals the loaded value of the length count. the next rising clock edge sets a ?ip-?op q0, shown in figure 48 . q0 is the leading bit of a 5-bit shift register. the outputs of this register can be programmed to control three events. ? the release of the open-drain done output ? the change of con?guration-related pins to the user function, activating all iobs. ? the termination of the global set/reset initialization of all clb and iob storage elements. the done pin can also be wire-anded with done pins of other fpgas or with other external signals, and can then be used as input to bit q3 of the start-up register. this is called start-up timing synchronous to done in and is selected by either cclk_sync or uclk_sync. when done is not used as an input, the operation is called start-up timing not synchronous to done in, and is selected by either cclk_nosync or uclk_nosync. as a con?guration option, the start-up control register beyond q0 can be clocked either by subsequent cclk pulses or from an on-chip user net called startup.clk. these signals can be accessed by placing the startup library symbol. start-up from cclk if cclk is used to drive the start-up, q0 through q3 pro- vide the timing. heavy lines in figure 47 show the default timing, which is compatible with xc2000 and xc3000 devices using early done and late reset. the thin lines indicate all other possible timing options.
r may 14, 1999 (version 1.6) 6-53 xc4000e and xc4000x series field programmable gate arrays 6 xc4000e/x uclk_sync xc4000e/x uclk_nosync xc4000e/x cclk_sync xc4000e/x cclk_nosync xc3000 xc2000 cclk gsr active uclk period done in done in di di+1 di+2 di di+1 di+2 u2 u3 u4 u2 u3 u4 u2 u3 u4 c1 synchronization uncertainty di di+1 di di+1 done i/o gsr active done i/o gsr active done c1 c2 c1 u2 c3 c4 c2 c3 c4 c2 c3 c4 i/o gsr active done i/o done global reset i/o done global reset i/o f = finished, no more configuration clocks needed daisy-chain lead device must have latest f heavy lines describe default timing cclk period length count match f f f f f f x9024 c1, c2 or c3 figure 47: start-up timing
r xc4000e and xc4000x series field programmable gate arrays 6-54 may 14, 1999 (version 1.6) start-up from a user clock (startup.clk) when, instead of cclk, a user-supplied start-up clock is selected, q1 is used to bridge the unknown phase relation- ship between cclk and the user clock. this arbitration causes an unavoidable one-cycle uncertainty in the timing of the rest of the start-up sequence. done goes high to signal end of con?guration xc4000 series devices read the expected length count from the bitstream and store it in an internal register. the length count varies according to the number of devices and the composition of the daisy chain. each device also counts the number of cclks during con?guration. two conditions have to be met in order for the done pin to go high: ? the chip's internal memory must be full, and ? the con?guration length count must be met, exactly . this is important because the counter that determines when the length count is met begins with the very ?rst cclk, not the ?rst one after the preamble. therefore, if a stray bit is inserted before the preamble, or the data source is not ready at the time of the ?rst cclk, the internal counter that holds the number of cclks will be one ahead of the actual number of data bits read. at the end of con?guration, the con?guration memory will be full, but the number of bits in the internal counter will not match the expected length count. as a consequence, a master mode device will continue to send out cclks until the internal counter turns over to zero, and then reaches the correct length count a second time. this will take several seconds [2 24 * cclk period] which is sometimes interpreted as the device not con?gur- ing at all. if it is not possible to have the data ready at the time of the ?rst cclk, the problem can be avoided by increasing the number in the length count by the appropriate value. the xact user guide includes detailed information about man- ually altering the length count. note that done is an open-drain output and does not go high unless an internal pull-up is activated or an external pull-up is attached. the internal pull-up is activated as the default by the bitstream generation software. release of user i/o after done goes high by default, the user i/o are released one cclk cycle after the done pin goes high. if cclk is not clocked after done goes high, the outputs remain in their initial state 3-stated, with a 50 k w - 100 k w pull-up. the delay from done high to active user i/o is controlled by an option to the bitstream generation software. release of global set/reset after done goes high by default, global set/reset (gsr) is released two cclk cycles after the done pin goes high. if cclk is not clocked twice after done goes high, all ?ip-?ops are held in their initial set or reset state. the delay from done high to gsr inactive is controlled by an option to the bitstream generation software. con?guration complete after done goes high three full cclk cycles are required after the done pin goes high, as shown in figure 47 on page 53 . if cclk is not clocked three times after done goes high, readback cannot be initiated and most boundary scan instructions cannot be used. con?guration through the boundary scan pins xc4000 series devices can be con?gured through the boundary scan pins. the basic procedure is as follows: ? power up the fpga with init held low (or drive the pr ogram pin low for more than 300 ns followed by a high while holding init low). holding init low allows enough time to issue the config command to the fpga. the pin can be used as i/o after con?guration if a resistor is used to hold init low. ? issue the config command to the tms input ? wait for init to go high ? sequence the boundary scan test access port to the shift-dr state ? toggle tck to clock data into tdi pin. the user must account for all tck clock cycles after init goes high, as all of these cycles affect the length count compare. for more detailed information, refer to the xilinx application note xapp017, boundary scan in xc4000 devices . this application note also applies to xc4000e and xc4000x devices.
r may 14, 1999 (version 1.6) 6-55 xc4000e and xc4000x series field programmable gate arrays 6 readback the user can read back the content of con?guration mem- ory and the level of certain internal nodes without interfer- ing with the normal operation of the device. readback not only reports the downloaded con?guration bits, but can also include the present state of the device, represented by the content of all ?ip-?ops and latches in clbs and iobs, as well as the content of function genera- tors used as rams. note that in xc4000 series devices, con?guration data is not inverted with respect to con?guration as it is in xc2000 and xc3000 families. xc4000 series readback does not use any dedicated pins, but uses four internal nets (rdbk.trig, rdbk.data, rdbk.rip and rdbk.clk) that can be routed to any iob. to access the internal readback signals, place the read- back library symbol and attach the appropriate pad sym- bols, as shown in figure 49 . after readback has been initiated by a high level on rdbk.trig after con?guration, the rdbk.rip (read in progress) output goes high on the next rising edge of rdbk.clk. subsequent rising edges of this clock shift out readback data on the rdbk.data net. readback data does not include the preamble, but starts with ?ve dummy bits (all high) followed by the start bit (low) of the ?rst frame. the ?rst two data bits of the ?rst frame are always high. each frame ends with four error check bits. they are read back as high. the last seven bits of the last frame are also read back as high. an additional start bit (low) and an 11-bit cyclic redundancy check (crc) signature follow, before rdbk.rip returns low. done * * * * ** qs r 1 0 0 1 1 0 1 0 1 0 0 1 gsr enable gsr invert startup.gsr startup.gts gts invert gts enable controlled by startup symbol in the user schematic (see libraries guide) global set/reset of all clb and iob flip-flop iobs operational per configuration global 3-state of all iobs q2 q3 q1/q4 done in startup q0 q1 q2 q3 q4 m m " finished " enables boundary scan, readback and controls the oscillator k sq k dq k dq k dq k dq full length count clear memory cclk startup.clk user net configuration bit options selected by user in "makebits" x1528 figure 48: start-up logic
r xc4000e and xc4000x series field programmable gate arrays 6-56 may 14, 1999 (version 1.6) readback options readback options are: read capture, read abort, and clock select. they are set with the bitstream generation software. read capture when the read capture option is selected, the readback data stream includes sampled values of clb and iob sig- nals. the rising edge of rdbk.trig latches the inverted values of the four clb outputs, the iob output ?ip-?ops and the input signals i1 and i2. note that while the bits describ- ing con?guration (interconnect, function generators, and ram content) are not inverted, the clb and iob output sig- nals are inverted. when the read capture option is not selected, the values of the capture bits re?ect the con?guration data originally written to those memory locations. if the ram capability of the clbs is used, ram data are available in readback, since they directly overwrite the f and g function-table con?guration of the clb. rdbk.trig is located in the lower-left corner of the device, as shown in figure 50 . read abort when the read abort option is selected, a high-to-low transition on rdbk.trig terminates the readback opera- tion and prepares the logic to accept another trigger. after an aborted readback, additional clocks (up to one readback clock per con?guration frame) may be required to re-initialize the control logic. the status of readback is indi- cated by the output control net rdbk.rip. rdbk.rip is high whenever a readback is in progress. clock select cclk is the default clock. however, the user can insert another clock on rdbk.clk. readback control and data are clocked on rising edges of rdbk.clk. if readback must be inhibited for security reasons, the readback control nets are simply not connected. rdbk.clk is located in the lower right chip corner, as shown in figure 50 . violating the maximum high and low time speci?cation for the readback clock the readback clock has a maximum high and low time speci?cation. in some cases, this speci?cation cannot be met. for example, if a processor is controlling readback, an interrupt may force it to stop in the middle of a readback. this necessitates stopping the clock, and thus violating the speci?cation. the speci?cation is mandatory only on clocking data at the end of a frame prior to the next start bit. the transfer mech- anism will load the data to a shift register during the last six clock cycles of the frame, prior to the start bit of the follow- ing frame. this loading process is dynamic, and is the source of the maximum high and low time requirements. therefore, the speci?cation only applies to the six clock cycles prior to and including any start bit, including the clocks before the ?rst start bit in the readback data stream. at other times, the frame data is already in the register and the register is not dynamic. thus, it can be shifted out just like a regular shift register. the user must precisely calculate the location of the read- back data relative to the frame. the system must keep track of the position within a data frame, and disable interrupts before frame boundaries. frame lengths and data formats are listed in ta b l e 1 9 , ta bl e 2 0 and ta bl e 2 1 . readback with the xchecker cable the xchecker universal download/readback cable and logic probe uses the readback feature for bitstream veri?- cation. it can also display selected internal signals on the pc or workstation screen, functioning as a low-cost in-cir- cuit emulator. readback data rip trig clk read_data obuf md1 md0 read_trigger ibuf x1786 if unconnected, default is cclk figure 49: readback schematic example i/o i/o i/o rdbk programmable interconnect rdclk i/o i/o x1787 trig data rip i figure 50: readback symbol in graphical editor
r may 14, 1999 (version 1.6) 6-57 xc4000e and xc4000x series field programmable gate arrays 6 xc4000e/ex/xl program readback switching characteristic guidelines testing of the switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are not measured directly. they are derived from benchmark timing patterns that are taken at device introduction, prior to any process improvements. the following guidelines re?ect worst-case values over the recommended operating conditions. note 1: timing parameters apply to all speed grades. note 2: if rdbk.trig is high prior to finished, finished will trigger the ?rst readback. note 1: timing parameters apply to all speed grades. note 2: if rdbk.trig is high prior to finished, finished will trigger the ?rst readback. rtrc t rcrt t rcrt t 2 2 rcl t 4 rcrr t 6 rch t 5 rcrd t 7 dummy dummy rdbk.data rdbk.rip rdclk.i rdbk.trig finished internal net valid x1790 valid 1 rtrc t 1 e/ex description symbol min max units rdbk.trig rdbk.trig setup to initiate and abort readback rdbk.trig hold to initiate and abort readback 1 2 t rtrc t rcrt 200 50 - - ns ns rdclk.1 rdbk.data delay rdbk.rip delay high time low time 7 6 5 4 t rcrd t rcrr t rch t rcl - - 250 250 250 250 500 500 ns ns ns ns xl description symbol min max units rdbk.trig rdbk.trig setup to initiate and abort readback rdbk.trig hold to initiate and abort readback 1 2 t rtrc t rcrt 200 50 - - ns ns rdclk.1 rdbk.data delay rdbk.rip delay high time low time 7 6 5 4 t rcrd t rcrr t rch t rcl - - 250 250 250 250 500 500 ns ns ns ns
r xc4000e and xc4000x series field programmable gate arrays 6-58 may 14, 1999 (version 1.6) table 22: pin functions during con?guration configuration mode slave serial <1:1:1> master serial <0:0:0> synch. peripheral <0:1:1> asynch. peripheral <1:0:1> master parallel down <1:1:0> master parallel up <1:0:0> user operation m2(high) (i) m2(low) (i) m2(low) (i) m2(high) (i) m2(high) (i) m2(high) (i) (i) m1(high) (i) m1(low) (i) m1(high) (i) m1(low) (i) m1(high) (i) m1(low) (i) (o) m0(high) (i) m0(low) (i) m0(high) (i) m0(high) (i) m0(low) (i) m0(low) (i) (i) hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) i/o ldc (low) ldc (low) ldc (low) ldc (low) ldc (low) ldc (low) i/o init init init init init init i/o done done done done done done done pr ogram (i) pr ogram (i) pr ogram (i) pr ogram (i) pr ogram (i) pr ogram (i) pr ogram cclk (i) cclk (o) cclk (i) cclk (o) cclk (o) cclk (o) cclk (i) rdy/ b usy (o) rdy/ b usy (o) rclk (o) rclk (o) i/o rs (i) i/o cs0 (i) i/o data 7 (i) data 7 (i) data 7 (i) data 7 (i) i/o data 6 (i) data 6 (i) data 6 (i) data 6 (i) i/o data 5 (i) data 5 (i) data 5 (i) data 5 (i) i/o data 4 (i) data 4 (i) data 4 (i) data 4 (i) i/o data 3 (i) data 3 (i) data 3 (i) data 3 (i) i/o data 2 (i) data 2 (i) data 2 (i) data 2 (i) i/o data 1 (i) data 1 (i) data 1 (i) data 1 (i) i/o din (i) din (i) data 0 (i) data 0 (i) data 0 (i) data 0 (i) i/o dout dout dout dout dout dout sgck4-gck5-i/o tdi tdi tdi tdi tdi tdi tdi-i/o tck tck tck tck tck tck tck-i/o tms tms tms tms tms tms tms-i/o tdo tdo tdo tdo tdo tdo tdo-(o) ws (i) a0 a0 i/o a1 a1 pgck4-gck6-i/o cs1 a2 a2 i/o a3 a3 i/o a4 a4 i/o a5 a5 i/o a6 a6 i/o a7 a7 i/o a8 a8 i/o a9 a9 i/o a10 a10 i/o a11 a11 i/o a12 a12 i/o a13 a13 i/o a14 a14 i/o a15 a15 sgck1-gck7-i/o a16 a16 pgck1-gck8-i/o a17 a17 i/o a18* a18* i/o a19* a19* i/o a20* a20* i/o a21* a21* i/o all others
r may 14, 1999 (version 1.6) 6-59 xc4000e and xc4000x series field programmable gate arrays 6 table 23: pin functions during con?guration configuration mode slave serial <1:1:1> master serial <0:0:0> synch. peripheral <0:1:1> asynch. peripheral <1:0:1> master parallel down <1:1:0> master parallel up <1:0:0> user operation m2(high) (i) m2(low) (i) m2(low) (i) m2(high) (i) m2(high) (i) m2(high) (i) (i) m1(high) (i) m1(low) (i) m1(high) (i) m1(low) (i) m1(high) (i) m1(low) (i) (o) m0(high) (i) m0(low) (i) m0(high) (i) m0(high) (i) m0(low) (i) m0(low) (i) (i) hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) hdc (high) i/o ldc (low) ldc (low) ldc (low) ldc (low) ldc (low) ldc (low) i/o init init init init init init i/o done done done done done done done pr ogram (i) pr ogram (i) pr ogram (i) pr ogram (i) pr ogram (i) pr ogram (i) pr ogram cclk (i) cclk (o) cclk (i) cclk (o) cclk (o) cclk (o) cclk (i) rdy/ b usy (o) rdy/ b usy (o) rclk (o) rclk (o) i/o rs (i) i/o cs0 (i) i/o data 7 (i) data 7 (i) data 7 (i) data 7 (i) i/o data 6 (i) data 6 (i) data 6 (i) data 6 (i) i/o data 5 (i) data 5 (i) data 5 (i) data 5 (i) i/o data 4 (i) data 4 (i) data 4 (i) data 4 (i) i/o data 3 (i) data 3 (i) data 3 (i) data 3 (i) i/o data 2 (i) data 2 (i) data 2 (i) data 2 (i) i/o data 1 (i) data 1 (i) data 1 (i) data 1 (i) i/o din (i) din (i) data 0 (i) data 0 (i) data 0 (i) data 0 (i) i/o dout dout dout dout dout dout sgck4-gck5-i/o tdi tdi tdi tdi tdi tdi tdi-i/o tck tck tck tck tck tck tck-i/o tms tms tms tms tms tms tms-i/o tdo tdo tdo tdo tdo tdo tdo-(o) ws (i) a0 a0 i/o a1 a1 pgck4-gck6-i/o cs1 a2 a2 i/o a3 a3 i/o a4 a4 i/o a5 a5 i/o a6 a6 i/o a7 a7 i/o a8 a8 i/o a9 a9 i/o a10 a10 i/o a11 a11 i/o a12 a12 i/o a13 a13 i/o a14 a14 i/o a15 a15 sgck1-gck7-i/o a16 a16 pgck1-gck8-i/o a17 a17 i/o a18* a18* i/o a19* a19* i/o a20* a20* i/o a21* a21* i/o all others * xc4000x only notes 1. a shaded table cell represents a 50 k w - 100 k w pull-up before and during con?guration. 2. (i) represents an input; (o) represents an output. 3. init is an open-drain output during con?guration.
r xc4000e and xc4000x series field programmable gate arrays 6-60 may 14, 1999 (version 1.6) con?guration timing the seven con?guration modes are discussed in detail in this section. timing speci?cations are included. slave serial mode in slave serial mode, an external signal drives the cclk input of the fpga. the serial con?guration bitstream must be available at the din input of the lead fpga a short setup time before each rising cclk edge. the lead fpga then presents the preamble dataand all data that over?ows the lead deviceon its dout pin. there is an internal delay of 0.5 cclk periods, which means that dout changes on the falling cclk edge, and the next fpga in the daisy chain accepts data on the sub- sequent rising cclk edge. figure 51 shows a full master/slave system. an xc4000 series device in slave serial mode should be connected as shown in the third device from the left. slave serial mode is selected by a <111> on the mode pins (m2, m1, m0). slave serial is the default mode if the mode pins are left unconnected, as they have weak pull-up resis- tors during con?guration. figure 52: slave serial mode programming switching characteristics xc4000e/x master serial xc4000e/x, xc5200 slave xc3100a slave xc1700d program note : m2, m1, m0 can be shorted to ground if not used as i/o note : m2, m1, m0 can be shorted to v cc if not used as i/o m2 m0 m1 dout cclk clk v cc +5 v data ce ceo vpp reset/oe done din ldc init init done program program d/p init reset cclk din cclk din dout dout m2 m0 m1 m1 pwrdn m0 m2 (low reset option used) 4.7 k 4.7 k 4.7 k 4.7 k 4.7 k 4.7 k 4.7 k v cc x9025 n/c n/c figure 51: master/slave serial mode circuit diagram 4 t cch bit n bit n + 1 bit n bit n - 1 3 t cco 5 t ccl 2 t ccd 1 t dcc din cclk dout (output) x5379 description symbol min max units cclk din setup 1 t dcc 20 ns din hold 2 t ccd 0ns din to dout 3 t cco 30 ns high time 4 t cch 45 ns low time 5 t ccl 45 ns frequency f cc 10 mhz note: con?guration must be delayed until the init pins of all daisy-chained fpgas are high.
r may 14, 1999 (version 1.6) 6-61 xc4000e and xc4000x series field programmable gate arrays 6 master serial mode in master serial mode, the cclk output of the lead fpga drives a xilinx serial prom that feeds the fpga din input. each rising edge of the cclk output increments the serial prom internal address counter. the next data bit is put on the sprom data output, connected to the fpga din pin. the lead fpga accepts this data on the subsequent rising cclk edge. the lead fpga then presents the preamble dataand all data that over?ows the lead deviceon its dout pin. there is an internal pipeline delay of 1.5 cclk periods, which means that dout changes on the falling cclk edge, and the next fpga in the daisy chain accepts data on the subsequent rising cclk edge. in the bitstream generation software, the user can specify fast con?grate, which, starting several bits into the ?rst frame, increases the cclk frequency by a factor of eight. for actual timing values please refer to con?guration switching characteristics on page 68 . be sure that the serial prom and slaves are fast enough to support this data rate. xc2000, xc3000/a, and xc3100a devices do not support the fast con?grate option. the sprom ce input can be driven from either ldc or done. using ldc avoids potential contention on the din pin, if this pin is con?gured as user-i/o, but ldc is then restricted to be a permanently high user output after con- ?guration. using done can also avoid contention on din, provided the early done option is invoked. figure 51 on page 60 shows a full master/slave system. the leftmost device is in master serial mode. master serial mode is selected by a <000> on the mode pins (m2, m1, m0). figure 53: master serial mode programming switching characteristics description symbol min max units cclk din setup 1 t dsck 20 ns din hold 2 t ckds 0ns notes: 1. at power-up, vcc must rise from 2.0 v to vcc min in less than 25 ms, otherwise delay con?guration by pulling pr ogram low until vcc is valid. 2. master serial mode timing is based on testing in slave mode. serial data in cclk (output) serial dout (output) 1 t dsck 2 t ckds n n + 1 n + 2 n ?3 n ?2 n ?1 n x3223
r xc4000e and xc4000x series field programmable gate arrays 6-62 may 14, 1999 (version 1.6) master parallel modes in the two master parallel modes, the lead fpga directly addresses an industry-standard byte-wide eprom, and accepts eight data bits just before incrementing or decre- menting the address outputs. the eight data bits are serialized in the lead fpga, which then presents the preamble dataand all data that over- ?ows the lead deviceon its dout pin. there is an inter- nal delay of 1.5 cclk periods, after the rising cclk edge that accepts a byte of data (and also changes the eprom address) until the falling cclk edge that makes the lsb (d0) of this byte appear at dout. this means that dout changes on the falling cclk edge, and the next fpga in the daisy chain accepts data on the subsequent rising cclk edge. the prom address pins can be incremented or decre- mented, depending on the mode pin settings. this option allows the fpga to share the prom with a wide variety of microprocessors and micro controllers. some processors must boot from the bottom of memory (all zeros) while oth- ers must boot from the top. the fpga is ?exible and can load its con?guration bitstream from either end of the mem- ory. master parallel up mode is selected by a <100> on the mode pins (m2, m1, m0). the eprom addresses start at 00000 and increment. master parallel down mode is selected by a <110> on the mode pins. the eprom addresses start at 3ffff and decrement. additional address lines in xc4000 devices the xc4000x devices have additional address lines (a18-a21) allowing the additional address space required to daisy-chain several large devices. the extra address lines are programmable in xc4000ex devices. by default these address lines are not activated. in the default mode, the devices are compatible with existing xc4000 and xc4000e products. if desired, the extra address lines can be used by specifying the address lines option in bitgen as 22 (bitgen -g addresslines:22). the lines (a18-a21) are driven when a master device detects, via the bitstream, that it should be using all 22 address lines. because these pins will initially be pulled high by internal pull-ups, designers using master parallel up mode should use external pull down resistors on pins a18-a21. if master parallel down mode is used external resistors are not necessary. all 22 address lines are always active in master parallel modes with xc4000xl devices. the additional address lines behave identically to the lower order address lines. if the address lines option in bitgen is set to 18, it will be ignored by the xc4000xl device. the additional address lines (a18-a21) are not available in the pc84 package. m0 m1 dout vcc m2 program d7 d6 d5 d4 d3 d2 d1 d0 program cclk din m0 m1 m2 dout program eprom (8k x 8) (or larger) a10 a11 a12 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 done d6 d5 d4 d3 d2 d1 d0 n/c n/c ce oe xc4000e/x slave 8 data bus cclk a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 init init . . . . . . . . . user control of higher order prom address bits can be used to select between alternative configurations done to din of optional daisy-chained fpgas a16 . . . a17 . . . high or low x9026 to cclk of optional daisy-chained fpgas 4.7k 4.7k note:m0 can be shorted to ground if not used as i/o. figure 54: master parallel mode circuit diagram
r may 14, 1999 (version 1.6) 6-63 xc4000e and xc4000x series field programmable gate arrays 6 figure 55: master parallel mode programming switching characteristics address for byte n byte 2 t drc address for byte n + 1 d7 d6 a0-a17 (output) d0-d7 rclk (output) cclk (output) dout (output) 1 t rac 7 cclks cclk 3 t rcd byte n - 1 x6078 description symbol min max units rclk delay to address valid 1 t rac 0 200 ns data setup time 2 t drc 60 ns data hold time 3 t rcd 0ns notes: 1. at power-up, vcc must rise from 2.0 v to vcc min in less than 25 ms, otherwise delay con?guration by pulling pr ogram low until vcc is valid. 2. the ?rst data byte is loaded and cclk starts at the end of the ?rst rclk active cycle (rising edge). this timing diagram shows that the eprom requirements are extremely relaxed. eprom access time can be longer than 500 ns. eprom data output has no hold-time requirements.
r xc4000e and xc4000x series field programmable gate arrays 6-64 may 14, 1999 (version 1.6) synchronous peripheral mode synchronous peripheral mode can also be considered slave parallel mode. an external signal drives the cclk input(s) of the fpga(s). the ?rst byte of parallel con?gura- tion data must be available at the data inputs of the lead fpga a short setup time before the rising cclk edge. subsequent data bytes are clocked in on every eighth con- secutive rising cclk edge. the same cclk edge that accepts data, also causes the rdy/ b usy output to go high for one cclk period. the pin name is a misnomer. in synchronous peripheral mode it is really an acknowledge signal. synchronous operation does not require this response, but it is a meaningful signal for test purposes. note that rdy/ b usy is pulled high with a high-impedance pullup prior to init going high. the lead fpga serializes the data and presents the pre- amble data (and all data that over?ows the lead device) on its dout pin. there is an internal delay of 1.5 cclk peri- ods, which means that dout changes on the falling cclk edge, and the next fpga in the daisy chain accepts data on the subsequent rising cclk edge. in order to complete the serial shift operation, 10 additional cclk rising edges are required after the last data byte has been loaded, plus one more cclk cycle for each daisy-chained device. synchronous peripheral mode is selected by a <011> on the mode pins (m2, m1, m0). x9027 control signals data bus program dout m0 m1 m2 d 0-7 init done program 4.7 k 4.7 k 4.7 k rdy/busy v cc optional daisy-chained fpgas note: m2 can be shorted to ground if not used as i/o cclk clock program dout xc4000e/x slave xc4000e/x synchro- nous peripheral m0 m1 n/c 8 m2 din init done cclk n/c figure 56: synchronous peripheral mode circuit diagram
r may 14, 1999 (version 1.6) 6-65 xc4000e and xc4000x series field programmable gate arrays 6 figure 57: synchronous peripheral mode programming switching characteristics 0 dout cclk 1 2 345 6 7 byte 0 byte 1 byte 0 out byte 1 out rdy/busy init 1 0 x6096 description symbol min max units cclk init (high) setup time t ic 5 m s d0 - d7 setup time t dc 60 ns d0 - d7 hold time t cd 0ns cclk high time t cch 50 ns cclk low time t ccl 60 ns cclk frequency f cc 8 mhz notes: 1. peripheral synchronous mode can be considered slave parallel mode. an external cclk provides timing, clocking in the ?rst data byte on the second rising edge of cclk after init goes high. subsequent data bytes are clocked in on every eighth consecutive rising edge of cclk. 2. the rdy/ b usy line goes high for one cclk period after data has been clocked in, although synchronous operation does not require such a response. 3. the pin name rdy/ b usy is a misnomer. in synchronous peripheral mode this is really an acknowledge signal. 4. note that data starts to shift out serially on the dout pin 0.5 cclk periods after it was loaded in parallel. therefore, additional cclk pulses are clearly required after the last byte has been loaded.
r xc4000e and xc4000x series field programmable gate arrays 6-66 may 14, 1999 (version 1.6) asynchronous peripheral mode write to fpga asynchronous peripheral mode uses the trailing edge of the logic and condition of ws and cs0 being low and rs and cs1 being high to accept byte-wide data from a micro- processor bus. in the lead fpga, this data is loaded into a double-buffered uart-like parallel-to-serial converter and is serially shifted into the internal logic. the lead fpga presents the preamble data (and all data that over?ows the lead device) on its dout pin. the rdy/ b usy output from the lead fpga acts as a hand- shake signal to the microprocessor. rdy/ b usy goes low when a byte has been received, and goes high again when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive new data. a new write may be started immediately, as soon as the rdy/ b usy output has gone low, acknowledging receipt of the previous data. write may not be terminated until rdy/ b usy is high again for one cclk period. note that rdy/ b usy is pulled high with a high-impedance pull-up prior to init going high. the length of the b usy signal depends on the activity in the uart. if the shift register was empty when the new byte was received, the b usy signal lasts for only two cclk periods. if the shift register was still full when the new byte was received, the b usy signal can be as long as nine cclk periods. note that after the last byte has been entered, only seven of its bits are shifted out. cclk remains high with dout equal to bit 6 (the next-to-last bit) of the last byte entered. the ready/ b usy handshake can be ignored if the delay from any one write to the end of the next write is guaran- teed to be longer than 10 cclk periods. status read the logic and condition of the cs0, cs1and rs inputs puts the device status on the data bus. ? d7 high indicates ready ? d7 low indicates busy ? d0 through d6 go unconditionally high it is mandatory that the whole start-up sequence be started and completed by one byte-wide input. otherwise, the pins used as write strobe or chip enable might become active outputs and interfere with the ?nal byte transfer. if this transfer does not occur, the start-up sequence is not com- pleted all the way to the ?nish (point f in figure 47 on page 53 ). in this case, at worst, the internal reset is not released. at best, readback and boundary scan are inhibited. the length-count value, as generated by the xact step soft- ware, ensures that these problems never occur. although rdy/ b usy is brought out as a separate signal, microprocessors can more easily read this information on one of the data lines. for this purpose, d7 represents the rdy/ b usy status when rs is low, ws is high, and the two chip select lines are both active. asynchronous peripheral mode is selected by a <101> on the mode pins (m2, m1, m0). address bus data bus address decode logic cs0 ... rdy/busy ws program d0? cclk dout din m2 m0 m1 n/c n/c n/c rs cs1 control signals init reprogram optional daisy-chained fpgas v cc done 8 x9028 4.7 k 4.7 k 4.7 k 4.7 k xc4000e/x asynchro- nous peripheral program cclk dout m2 m0 m1 init done xc4000e/x slave figure 58: asynchronous peripheral mode circuit diagram
r may 14, 1999 (version 1.6) 6-67 xc4000e and xc4000x series field programmable gate arrays 6 figure 59: asynchronous peripheral mode programming switching characteristics previous byte d6 d7 d0 d1 d2 1 t ca 2 t dc 4 t wtrb 3 t cd 6 t busy ready busy rs, cs0 ws, cs1 d7 ws/cs0 rs, cs1 d0-d7 cclk rdy/busy dout write to lca read status x6097 7 4 description symbol min max units write effective write time ( cs0, ws=low; rs, cs1=high) 1t ca 100 ns din setup time 2 t dc 60 ns din hold time 3 t cd 0ns rdy rdy/ busy delay after end of write or read 4t wtrb 60 ns rdy/ busy active after beginning of read 760ns rdy/ busy low output (note 4) 6 t busy 2 9 cclk periods notes: 1. con?guration must be delayed until the init pins of all daisy-chained fpgas are high. 2. the time from the end of ws to cclk cycle for the new byte of data depends on the completion of previous byte processing and the phase of the internal timing generator for cclk. 3. cclk and dout timing is tested in slave mode. 4. t busy indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. the shortest t busy occurs when a byte is loaded into an empty parallel-to-serial converter. the longest t busy occurs when a new word is loaded into the input register before the second-level buffer has started shifting out data this timing diagram shows very relaxed requirements. data need not be held beyond the rising edge of ws .rdy/ b usy will go active within 60 ns after the end of ws . a new write may be asserted immediately after rdy/ b usy goes low, but write may not be terminated until rdy/ b usy has been high for one cclk period.
r xc4000e and xc4000x series field programmable gate arrays 6-68 may 14, 1999 (version 1.6) con?guration switching characteristics master modes (xc4000e/ex) master modes (xc4000xl) slave and peripheral modes (all) description symbol min max units power-on reset m0 = high t por 10 40 ms m0 = low t por 40 130 ms program latency t pi 30 200 m s per clb column cclk (output) delay t icck 40 250 m s cclk (output) period, slow t cclk 640 2000 ns cclk (output) period, fast t cclk 80 250 ns description symbol min max units power-on reset m0 = high t por 10 40 ms m0 = low t por 40 130 ms program latency t pi 30 200 m s per clb column cclk (output) delay t icck 40 250 m s cclk (output) period, slow t cclk 540 1600 ns cclk (output) period, fast t cclk 67 200 ns description symbol min max units power-on reset t por 10 33 ms program latency t pi 30 200 m s per clb column cclk (input) delay (required) t icck 4 m s cclk (input) period (required) t cclk 100 ns valid program init vcc pi t por t icck t cclk t cclk output or input m0, m1, m2 done response <300 ns <300 ns >300 ns re-program x1532 (required) i/o
r may 14, 1999 (version 1.6) 6-69 xc4000e and xc4000x series field programmable gate arrays 6 product availability ta b l e 2 4 , ta b l e 2 5 , and ta bl e 2 6 show the planned packages and speed grades for xc4000-series devices. call your local sales of?ce for the latest availability information, or see the xilinx w eb linx at http://www.xilinx.com for the latest revision of the speci?cations. table 24: component availability chart for xc4000xl fpgas pins 84 100 100 144 144 160 160 176 176 208 208 240 240 256 299 304 352 411 432 475 559 560 type plast. plcc plast. pqfp plast. vqfp plast. tqfp high-perf. tqfp high-perf. qfp plast. pqfp plast. tqfp high-perf. tqfp high-perf. qfp plast. pqfp high-perf. qfp plast. pqfp plast. bga ceram. pga high-perf. qfp plast. bga ceram. pga plast. bga ceram. pga ceram. pga plast. bga code pc84 pq100 vq100 tq144 ht144 hq160 pq160 tq176 ht176 hq208 pq208 hq240 pq240 bg256 pg299 hq304 bg352 pg411 bg432 pg475 pg559 bg560 xc4002xl -3 c i c i c i -2 c i c i c i -1 c i c i c i -09c ccc xc4005xl -3 c ic ic ic i c i c i -2 c i c c i c i c i c i -1 c i c i c i c i c i c i -09c cccc c c xc4010xl -3 c i c i c i c i c i c i c i -2 c i c i c i c i c i c i c i -1 c i c i c i c i c i c i c i -09c c c c c c c c xc4013xl -3 c i c i c i c i c i c i -2 c i c i c i c i c i c i -1 c i c i c i c i c i c i -09c cccccc -08c cccccc xc4020xl -3 c i c i c i c i c i c i -2 c i c i c i c i c i c i -1 c i c i c i c i c i c i -09c cccccc xc4028xl -3 c i c i c i c i c i c i c i -2 c i c i c i c i c i c i c i -1 c i c i c i c i c i c i c i -09c c c c cccc xc4036xl -3 c i c i c i c i c i c i c i -2 c i c i c c i c i c i c i -1 c i c i c i c i c i c i c i -09c ccccccc -08c ccccccc xc4044xl -3 c i c i c i c i c i c i c i -2 c i c i c i c i c i c i c i -1 c i c i c i c i c i c i c i -09c ccccccc xc4052xl -3 c i c i c i c i c i -2 c i c i c i c i c i -1 c i c i c i c i c i -09c ccccc xc4062xl -3 c i c i c i c i c i -2 c i c i c i c i c i -1 c i c i c i c i c i -09c ccccc -08c ccccc xc4085xl -3 c i c i c i -2 c i c i c i -1 c i c i c i -09c ccc 1/29/99 c = commercial t j = 0 to +85 c i= industrial t j = -40 c to +100 c
r xc4000e and xc4000x series field programmable gate arrays 6-70 may 14, 1999 (version 1.6) table 25: component availability chart for xc4000e fpgas pins 84 100 100 120 144 156 160 191 208 208 223 225 240 240 299 304 type plast. plcc plast. pqfp plast. vqfp ceram. pga plast. tqfp ceram. pga plast. pqfp ceram. pga high-perf. qfp plast. pqfp ceram. pga plast. bga high-perf. qfp plast. pqfp ceram. pga high-perf. qf code pc84 pq100 vq100 pg120 tq144 pg156 pq160 pg191 hq208 pq208 pg223 bg225 hq240 pq240 pg299 hq304 xc4003e -4 c i c i c i c i -3 c i c i c i c i -2 c i c i c i c i -1cccc xc4005e -4 c i c i c i c i c i c i -3 c i c i c i c i c i c i -2 c i c i c i c i c i c i -1cc ccc c xc4006e -4 c i c i c i c i c i -3 c i c i c i c i c i -2 c i c i c i c i c i -1c ccc c xc4008e -4 c i c i c i c i -3 c i c i c i c i -2 c i c i c i c i -1 c c c c xc4010e -4 c i c i c i c i c i c i -3 c i c i c i c i c i c i -2 c i c i c i c i c i c i -1c cccc c xc4013e -4 c i c i c i c i c i c i c i -3 c i c i c i c i c i c i c i -2 c i c i c i c i c i c i c i -1 c cccccc xc4020e -4 c i c i c i -3 c i c i c i -2 c i c i c i -1 ccc xc4025e -4 c i c i c i c i -3 c i c i c i c i -2 cccc 1/29/99 c = commercial t j = 0 to +85 c i= industrial t j = -40 c to +100 c table 26: component availability chart for xc4000ex fpgas pins 208 240 299 304 352 411 432 type high-perf. qfp high-perf. qfp ceram. pga high-perf. qfp plast. bga ceram. pga plast. bga code hq208 hq240 pg299 hq304 bg352 pg411 bg432 xc4028ex -4 c i c i c i c i c i -3 c i c i c i c i c i -2ccccc xc4036ex -4 c i c i c i c i c i -3 c i c i c i c i c i -2 c c c c c 1/29/99 c = commercial t j = 0 to +85 c i= industrial t j = -40 c to +100 c
r may 14, 1999 (version 1.6) 6-71 xc4000e and xc4000x series field programmable gate arrays 6 user i/o per package ta b l e 2 7 , ta bl e 2 8 , and ta b l e 2 9 show the number of user i/os available in each package for xc4000-series devices. call your local sales of?ce for the latest availability information, or see the xilinx w eb linx at http://www.xilinx.com for the latest revision of the speci?cations. table 27: user i/o chart for xc4000xl fpgas max i/o maximum user accessible i/o by package type device pc84 pq100 vq100 tq144 ht144 hq160 pq160 tq176 ht176 hq208 pq208 hq240 pq240 bg256 pg299 hq304 bg352 pg411 bg432 pg475 pg559 bg560 xc4002xl 64 61 64 64 xc4005xl 112 61 77 77 112 112 112 xc4010xl 160 61 77 113 129 145 160 160 xc4013xl 192 113 129 145 160 192 192 xc4020xl 224 113 129 145 160 192 205 xc4028xl 256 129 160 193 205 256 256 256 xc4036xl 288 129 160 193 256 288 288 288 xc4044xl 320 129 160 193 256 289 320 320 xc4052xl 352 193 256 352 352 352 xc4062xl 384 193 256 352 384 384 xc4085xl 448 352 448 448 1/29/99 table 28: user i/o chart for xc4000e fpgas max i/o maximum user accessible i/o by package type device pc84 pq100 vq100 pg120 tq144 pg156 pq160 pg191 hq208 pq208 pg223 bg225 hq240 pq240 pg299 hq304 xc4003e 80 61 77 77 80 xc4005e 112 61 77 112 112 112 112 xc4006e 128 61 113 125 128 128 xc4008e 144 61 129 144 144 xc4010e 160 61 129 160 160 160 160 xc4013e 192 129 160 160 192 192 192 192 xc4020e 224 160 192 193 xc4025e 256 192 193 256 256 1/29/99 table 29: user i/o chart for xc4000ex fpgas max i/o maximum user accessible i/o by package type device hq208 hq240 pg299 hq304 bg352 pg411 bg432 xc4028ex 256 160 193 256 256 256 xc4036ex 288 193 256 288 288 288 1/29/99
r xc4000e and xc4000x series field programmable gate arrays 6-72 may 14, 1999 (version 1.6) xc4000 series electrical characteristics and device-speci?c pinout table for the latest electrical characteristics and package/pinout information for each xc4000 family, see the xilinx web site at http://www .xilinx.com/par tinf o/databook.htm#xc4000 ordering information xc4013e-3hq240c device type speed grade -6 -5 -4 -3 -2 -1 number of pins package type temperature range c = commercial (t j = 0 to +85 c) i = industrial (t j = -40 to +100 c) m = military (t c = -55 to+125 c) pc = plastic lead chip carrier pq = plastic quad flat pack vq = very thin quad flat pack tq = thin quad flat pack bg = ball grid array pg = ceramic pin grid array hq = high heat dissipation quad flat pack mq = metal quad flat pack cb = top brazed ceramic quad flat pack x9020 example: revision control version description 3/30/98 (1.5) updated xc4000xl timing and added xc4002xl 1/29/99 (1.5) updated pin diagrams 5/14/99 (1.6) replaced electrical specification and pinout pages for e, ex, and xl families with separate updates and added url link for electrical specifications/pinouts for weblinx users
r ds005 (v. 1.8 october 18, 1999 - product speci?cation 6-73 xc4000e and xc4000x series field programmable gate arrays 6 xc4000xl electrical speci?cations de?nition of terms in the following tables, some speci?cations may be designated as advance or preliminary. these terms are de?ned as follows: advance: initial estimates based on simulation and/or extrapolation from other speed grades, devices, or devicefamilies. values are subject to change. use as estimates, not for production. preliminary: based on preliminary characterization. further changes are not expected. unmarked: speci?cations not identi?ed as either advance or preliminary are to be considered final. except for pin-to-pin input and output parameters, the a.c. parameter delay speci?cations included in this document are derived from measuring internal test patterns. all speci?cations are representative of worst-case supply voltage and junction temperature conditions. all speci?cations subject to change without notice. xc4000xl d.c. characteristics absolute maximum ratings recommended operating conditions description units v cc supply voltage relative to ground -0.5 to 4.0 v v in input voltage relative to ground (note 1) -0.5 to 5.5 v v ts voltage applied to 3-state output (note 1) -0.5 to 5.5 v v cct longest supply voltage rise time from 1 v to 3v 50 ms t stg storage temperature (ambient) -65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 c t j junction temperature ceramic packages +150 c plastic packages +125 c note 1: maximum dc excursion above v cc or below ground must be limited to either 0.5 v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to -2.0 v or overshoot tov cc +2.0 v, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under recommended operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol description min max units v cc supply voltage relative to gnd, t j = 0 c to +85 c commercial 3.0 3.6 v supply voltage relative to gnd, t j = -40 c to +100 c industrial 3.0 3.6 v v ih high-level input voltage 50% of v cc 5.5 v v il low-level input voltage 0 30% of v cc v t in input signal transition time 250 ns notes: at junction temperatures above those listed above, all delay parameters increase by 0.35% per c. input and output measurement threshold is ~50% of v cc .
r xc4000e and xc4000x series field programmable gate arrays 6-74 ds005 (v. 1.8 october 18, 1999 - product speci?cation d.c. characteristics over recommended operating conditions power-0n power supply requirements xilinx fpgas require a minimum rated power supply current capacity to insure proper initialization, and the power supply ramp-up time does affect the current required. a fast ramp-up time requires more current than a slow ramp-up time. the slowest ramp-up time is 50 ms. current capacity is not speci?ed for a ramp-up time faster than 2ms. the current capacity varies linealy with ramp-up time, e.g. , an xc4036xl with a ramp-up time of 25 ms would require a capacity predicted by the point on the straight line drawn from 1a at 120 m s to 500 ma at 50 ms at the 25 ms time mark. this point is approximately 750 ma . symbol description min max units v oh high-level output voltage @ i oh = -4.0 ma, v cc min (lvttl) 2.4 v high-level output voltage @ i oh = -500 m a, (lvcmos) 90% v cc v v ol low-level output voltage @ i ol = 12.0 ma, v cc min (lvttl) (note 1) 0.4 v low-level output voltage @ i ol = 1500 m a, (lvcmos) 10% v cc v v dr data retention supply voltage (below which configuration data may be lost) 2.5 v i cco quiescent fpga supply current (note 2) 5 ma i l input or output leakage current -10 +10 m a c in input capacitance (sample tested) bga, sbga, pq, hq, mq packages 10 pf pga packages 16 pf i rpu pad pull-up (when selected) @ v in = 0 v (sample tested) 0.02 0.25 ma i rpd pad pull-down (when selected) @ v in = 3.6 v (sample tested) 0.02 0.15 ma i rll horizontal longline pull-up (when selected) @ logic low 0.3 2.0 ma note 1: with up to 64 pins simultaneously sinking 12 ma. note 2: with no output current loads, no active input or longline pull-up resistors, all i/o pins tri-stated and ?oating. product description ramp-up time fast (120 m s) slow (50 ms) xc4005 - 36xl minimum required current supply 1 a 500 ma xc4044- 62xl minimum required current supply 2 a 500 ma xc4085xl 1 minimum required current supply 2 a 1 500 ma notes: 1. the xc4085xl fast ramp-up time is 5 ms. devices are guaranteed to initialize properly with the minimum current listed above. a larger capacity power supply may result in a larger initialization current. this speci?cation applies to commercial and industrial grade products only. ramp-up time is measured from 0 v dc to 3.6 v dc . peak current required lasts less than 3 ms, and occurs near the internal power on reset threshold voltage. after initialization and before con?guration, i cc max is less than 10 ma.
r ds005 (v. 1.8 october 18, 1999 - product speci?cation 6-75 xc4000e and xc4000x series field programmable gate arrays 6 xc4000xl a.c. characteristics testing of the switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb ?ip-?ops are clocked by the global clock net. when fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature. values apply to all xc4000xl devices and are expressed in nanoseconds unless otherwise noted. global low skew buffer to clock k speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max delay from pad through gls buffer to any clock input, k t gls xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 0.3 0.4 0.5 0.6 0.7 0.9 1.1 1.2 1.3 1.4 1.6 2.1 2.7 3.2 3.6 4.0 4.4 4.8 5.3 5.7 6.3 7.2 1.8 2.3 2.8 3.1 3.5 3.8 4.2 4.6 5.0 5.4 6.2 1.6 2.0 2.4 2.7 3.0 3.3 3.6 4.0 4.5 4.7 5.7 1.5 1.9 2.3 2.6 2.9 3.2 3.5 3.9 4.4 4.6 5.5 2.3 3.1 4.0 ns ns ns ns ns ns ns ns ns ns ns
r xc4000e and xc4000x series field programmable gate arrays 6-76 ds005 (v. 1.8 october 18, 1999 - product speci?cation global early bufges 1, 2, 5, and 6 to iob clock global early bufges 3, 4, 7, and 8 to iob clock speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max delay from pad through ge buffer to any iob clock input. t ge xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 0.1 0.3 0.3 0.4 0.4 0.3 0.3 0.2 0.3 0.3 0.4 1.6 1.9 2.2 2.4 2.6 2.8 3.1 3.5 4.0 4.9 5.8 1.4 1.8 1.9 2.1 2.2 2.4 2.7 3.0 3.5 4.3 5.1 1.3 1.7 1.7 1.8 2.1 2.1 2.3 2.6 3.0 3.7 4.7 1.2 1.6 1.7 1.7 2.0 2.0 2.2 2.4 3.0 3.4 4.3 1.5 1.9 3.0 ns ns ns ns ns ns ns ns ns ns ns speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max delay from pad through ge buffer to any iob clock input. t ge xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 0.5 0.7 0.7 0.7 0.8 0.9 0.9 1.0 1.1 1.2 1.3 2.8 3.1 3.5 3.8 4.1 4.4 4.7 5.1 5.5 5.9 6.8 2.5 2.8 3.1 3.3 3.6 3.9 4.2 4.5 4.8 5.2 6.0 2.1 2.7 2.8 2.9 3.4 3.4 3.7 4.0 4.3 4.8 5.5 1.7 2.5 2.7 2.8 3.2 3.3 3.6 3.7 4.3 4.5 5.2 2.4 3.1 4.0 ns ns ns ns ns ns ns ns ns ns ns
r ds005 (v. 1.8 october 18, 1999 - product speci?cation 6-77 xc4000e and xc4000x series field programmable gate arrays 6 xc4000xl clb characteristics testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000xl devices and are expressed in nanoseconds unless otherwise noted. clb switching characteristic guidelines speed grade -3 -2 -1 -09 -08 description symbol min max min max min max min max min max combinatorial delays f/g inputs to x/y outputs f/g inputs via h to x/y outputs f/g inputs via transparent latch to q outputs c inputs via sr/h0 via h to x/y outputs c inputs via h1 via h to x/y outputs c inputs via din/h2 via h to x/y outputs c inputs via ec, din/h2 to yq, xq output (bypass) t ilo t iho t ito t hh0o t hh1o t hh2o t cbyp 1.6 2.7 2.9 2.5 2.4 2.5 1.5 1.5 2.4 2.6 2.2 2.1 2.2 1.3 1.3 2.2 2.2 2.0 1.9 2.0 1.1 1.2 2.0 2.0 1.8 1.6 1.8 1.0 1.1 1.9 1.8 1.8 1.5 1.8 0.9 clb fast carry logic operand inputs (f1, f2, g1, g4) to c out add/subtract input (f3) to c out initialization inputs (f1, f3) to c out c in through function generators to x/y outputs c in to c out , bypass function generators carry net delay, c out to c in t opcy t ascy t incy t sum t byp t net 2.7 3.3 2.0 2.8 0.26 0.32 2.3 2.9 1.8 2.6 0.23 0.28 2.0 2.5 1.5 2.4 0.20 0.25 1.6 1.8 1.0 1.7 0.14 0.24 1.6 1.8 0.9 1.5 0.14 0.24 sequential delays clock k to flip-flop outputs q clock k to latch outputs q t cko t cklo 2.1 2.1 1.9 1.9 1.6 1.6 1.5 1.5 1.4 1.4 setup time before clock k f/g inputs f/g inputs via h c inputs via h0 through h c inputs via h1 through h c inputs via h2 through h c inputs via din c inputs via ec c inputs via s/r, going low (inactive) cin input via f/g cin input via f/g and h t ick t ihck t hh0ck t hh1ck t hh2ck t dick t ecck t rck t cck t chck 1.1 2.2 2.0 1.9 2.0 0.9 1.0 0.6 2.3 3.4 1.0 1.9 1.7 1.6 1.7 0.8 0.9 0.5 2.1 3.0 0.9 1.7 1.6 1.4 1.6 0.7 0.8 0.5 1.9 2.7 0.8 1.6 1.4 1.2 1.4 0.6 0.7 0.4 1.3 2.1 0.8 1.5 1.4 1.1 1.4 0.6 0.7 0.4 1.2 2.0 hold time after clock k f/g inputs f/g inputs via h c inputs via sr/h0 through h c inputs via h1 through h c inputs via din/h2 through h c inputs via din/h2 c inputs via ec c inputs via sr, going low (inactive) t cki t ckih t ckhh0 t ckhh1 t ckhh2 t ckdi t ckec t ckr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clock clock high time clock low time t ch t cl 3.0 3.0 2.8 2.8 2.5 2.5 2.3 2.3 2.1 2.1 set/reset direct width (high) delay from c inputs via s/r, going high to q t rpw t rio 3.0 3.7 2.8 3.2 2.5 2.8 2.3 2.7 2.3 2.6 global set/reset minimum gsr pulse width t mrw 19.8 17.3 15.0 14.0 14.0 delay from gsr input to any q t mrq see table on page 85 for t rri values per device. toggle frequency (mhz) (for export control) f tog (mhz) 166 179 200 217 238
r xc4000e and xc4000x series field programmable gate arrays 6-78 ds005 (v. 1.8 october 18, 1999 - product speci?cation clb single-port ram synchronous (edge-triggered) write operation guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000xl devices and are expressed in nanoseconds unless otherwise noted. single port ram speed grade -3 -2 -1 -09 -08 size symbol min max min max min max min max min max write operation address write cycle time (clock k period) 16x2 32x1 t wcs t wcts 9.0 9.0 8.4 8.4 7.7 7.7 7.4 7.4 7.4 7.4 clock k pulse width (active edge) 16x2 32x1 t wps t wpts 4.5 4.5 4.2 4.2 3.9 3.9 3.7 3.7 3.7 3.7 address setup time before clock k 16x2 32x1 t ass t asts 2.2 2.2 2.0 2.0 1.7 1.7 1.7 1.7 1.6 1.7 address hold time after clock k 16x2 32x1 t ahs t ahts 0 0 0 0 0 0 0 0 0 0 din setup time before clock k 16x2 32x1 t dss t dsts 2.0 2.5 1.9 2.3 1.7 2.1 1.7 2.1 1.7 2.1 din hold time after clock k 16x2 32x1 t dhs t dhts 0 0 0 0 0 0 0 0 0 0 we setup time before clock k 16x2 32x1 t wss t wsts 2.0 1.8 1.8 1.7 1.6 1.5 1.6 1.5 1.6 1.5 we hold time after clock k 16x2 32x1 t whs t whts 0 0 0 0 0 0 0 0 0 0 data valid after clock k 16x2 32x1 t wos t wots 6.8 8.1 6.3 7.5 5.8 6.9 5.8 6.7 5.7 6.7 read operation address read cycle time 16x2 32x1 t rc t rct 4.5 6.5 3.1 5.5 2.6 3.8 2.6 3.8 2.6 3.8 data valid after address change (no write enable) 16x2 32x1 t ilo t iho 1.6 2.7 1.5 2.4 1.3 2.2 1.2 2.0 1.1 1.9 address setup time before clock k 16x2 32x1 t ick t ihck 1.1 2.2 1.0 1.9 0.9 1.7 0.8 1.6 0.8 1.5
r ds005 (v. 1.8 october 18, 1999 - product speci?cation 6-79 xc4000e and xc4000x series field programmable gate arrays 6 clb dual-port ram synchronous (edge-triggered) write operation guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000xl devices and are expressed in nanoseconds unless otherwise noted. clb ram synchronous (edge-triggered) write timing waveforms dual port ram speed grade -3 -2 --1 -09 -08 size symbol min max min max min max min max min max address write cycle time (clock k period) clock k pulse width (active edge) address setup time before clock k address hold time after clock k din setup time before clock k din hold time after clock k we setup time before clock k we hold time after clock k data valid after clock k 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 t wcds t wpds t asds t ahds t dsds t dhds t wsds t whds t wods 9.0 4.5 2.5 0 2.5 0 1.8 0 7.8 8.4 4.2 2.0 0 2.3 0 1.7 0 7.3 7.7 3.9 1.7 0 2.0 0 1.6 0 6.7 7.4 3.7 1.7 0 2.0 0 1.6 0 6.7 7.4 3.7 1.6 0 2.0 0 1.6 0 6.6 x6461 wclk (k) we address data in data out old new t dss t dhs t ass t ahs t wss t wps t whs t wos t ilo t ilo wclk (k) we address data in t dsds t dhds t asds t ahds t wsds t wpds t whds x6474 data out old new t wods t ilo t ilo single-port ram dual-port ram
r xc4000e and xc4000x series field programmable gate arrays 6-80 ds005 (v. 1.8 october 18, 1999 - product speci?cation xc4000xl pin-to-pin output parameter guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values are expressed in nanoseconds unless otherwise noted. output flip-flop, clock to out capacitive load factor figure 60 shows the relationship between i/o output delay and load capacitance. it allows a user to adjust the speci- ?ed output delay if the load capacitance is different than 50 pf. for example, if the actual load capacitance is 120 pf, add 2.5 ns to the speci?ed delay. if the load capac- itance is 20 pf, subtract 0.8 ns from the speci?ed output delay. figure 60 is usable over the speci?ed operating conditions of voltage and temperature and is independent of the out- put slew rate control. figure 60: delay factor at various capacitive loads speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max global low skew clock to output us- ing output flip flop t ickof xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 1.2 1.3 1.4 1.5 1.6 1.8 2.0 2.1 2.2 2.3 2.5 7.1 7.7 8.2 8.6 9.0 9.4 9.8 10.3 10.7 11.3 12.2 6.1 6.6 7.1 7.4 7.8 8.1 8.5 8.9 9.3 9.7 10.5 5.4 5.8 6.2 6.5 6.8 7.1 7.4 7.8 8.3 8.5 9.5 5.1 5.4 5.8 6.1 6.4 6.7 7.0 7.4 7.9 8.1 9.0 5.6 6.4 7.3 ns ns ns ns ns ns ns ns ns ns ns for output slow option add t slow all devices 0.5 3.0 2.5 2.0 1.7 1.6 ns notes: clock-to-out minimum delay is measured with the fastest route and the lightest load, clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (ik or ok) per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be added to the ac parameter tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for fast mode con?gurations. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. for different loads, see figure 1. x8257 -2 0 20406080 capacitance (pf) delta delay (ns) 100 120 140 -1 0 1 2 3
r ds005 (v. 1.8 october 18, 1999 - product speci?cation 6-81 xc4000e and xc4000x series field programmable gate arrays 6 output flip-flop, clock to out, bufge #s 1, 2, 5, and 6 output flip-flop, clock to out, bufge #s 3, 4, 7, and 8 speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max global early clock to output using output flip flop. values are for buf- ge #s 1, 2, 5, and 6. t ickeof xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 1.0 1.2 1.2 1.3 1.3 1.2 1.2 1.1 1.2 1.2 1.3 6.6 6.9 7.2 7.4 7.6 7.8 8.1 8.5 9.0 9.9 10.8 5.7 6.1 6.2 6.4 6.5 6.7 7.0 7.3 7.8 8.6 9.4 5.1 5.5 5.5 5.6 5.9 5.9 6.1 6.4 6.8 7.5 8.5 4.8 5.2 5.3 5.3 5.6 5.6 5.8 6.0 6.6 7.0 7.9 4.8 5.2 6.3 ns ns ns ns ns ns ns ns ns ns ns notes: clock-to-out minimum delay is measured with the fastest route and the lightest load, clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (ik or ok) per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be added to the ac parameter tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for fast mode con?gurations. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. for different loads, see figure 1. speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max global early clock to output using output flip flop. values are for buf- ge #s 3, 4, 7, and 8. t ickeof xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 1.3 1.5 1.6 1.6 1.7 1.7 1.8 1.9 2.0 2.0 2.2 7.8 8.1 8.5 8.8 9.1 9.4 9.7 10.1 10.5 10.9 11.8 6.8 7.1 7.4 7.6 7.9 8.2 8.5 8.8 9.1 9.5 10.3 5.9 6.5 6.6 6.7 7.2 7.2 7.5 7.8 8.1 8.6 9.3 5.3 6.1 6.3 6.4 6.8 6.9 7.2 7.3 7.9 8.1 8.8 5.7 6.4 7.3 ns ns ns ns ns ns ns ns ns ns ns notes: clock-to-out minimum delay is measured with the fastest route and the lightest load, clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (ik or ok) per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be added to the ac parameter tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for fast mode con?gurations. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. for different loads, see figure 1.
r xc4000e and xc4000x series field programmable gate arrays 6-82 ds005 (v. 1.8 october 18, 1999 - product speci?cation xc4000xl pin-to-pin input parameter guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values are expressed in nanoseconds unless otherwise noted global low skew clock, set-up and hold speed grade -3 -2 -1 -09 -08 units description symbol device min min min min min input setup and hold times no delay global low skew clock and iff global low skew clock and fcl t psn /t phn xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 2.5 / 1.5 1.2 / 2.6 1.2 / 3.0 1.2 / 3.2 1.2 / 3.7 1.2 / 4.4 1.2 / 5.5 1.2 / 5.8 1.2 / 7.1 1.2 / 7.0 1.2 / 9.4 2.2 / 1.3 1.1 / 2.2 1.1 / 2.6 1.1 / 2.8 1.1 / 3.2 1.1 / 3.8 1.1 / 4.8 1.1 / 5.0 1.1 / 6.2 1.1 / 6.1 1.1 / 8.2 1.9 / 1.2 0.9 / 2.0 0.9 / 2.3 0.9 / 2.4 0.9 / 2.8 0.9 / 3.3 0.9 / 4.1 0.9 / 4.4 0.9 / 5.4 0.9 / 5.3 0.9 / 7.1 1.7 / 1.0 0.8 / 1.7 0.8 / 2.0 0.8 / 2.1 0.8 / 2.4 0.8 / 2.9 0.8 / 3.6 0.8 / 3.8 0.8 / 4.7 0.8 / 4.6 0.8 / 6.2 0.8 / 2.1 0.8 / 3.6 0.8 / 4.6 ns ns ns ns ns ns ns ns ns ns ns partial delay global low skew clock and iff global low skew clock and fcl t psp /t php xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 8.4 / 0.0 10. 5 / 0.0 11.1 / 0.0 6.1 / 1.0 11.9 / 1.0 12.3 / 1.0 6.4 / 1.0 13.1 / 1.0 11.9 / 1.0 6.7 / 1.2 12.9 / 1.2 7.3 / 0.0 9.1 / 0.0 9.7 / 0.0 5.3 / 1.0 10.3 / 1.0 10.7 / 1.0 5.6 / 1.0 11.4 / 1.0 10.3 / 1.0 5.8 / 1.2 11.2 / 1.2 6.3 / 0.0 7.9 / 0.0 8.4 / 0.0 4.6 / 1.0 9.0 / 1.0 9.3 / 1.0 4.8 / 1.0 9.9 / 1.0 9.0 / 1.0 5.1 / 1.2 9.8 / 1.2 5.5 / 0.0 6.9 / 0.0 7.3 / 0.0 4.0 / 1.0 7.8 / 1.0 8.1 / 1.0 4.2 / 1.0 8.6 / 1.0 7.8 / 1.0 4.4 / 1.2 8.5 / 1.2 3.7 / 0.5 4.0/ 0.8 4.2/ 1.0 ns ns ns ns ns ns ns ns ns ns ns full delay global low skew clock and iff t psd /t phd xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 6.8 / 0.0 8.8 / 0.0 9.0 / 0.0 6.4 / 0.0 8.8 / 0.0 9.3 / 0.0 6.6 / 0.0 10.6 / 0.0 11.2 / 0.0 6.8 / 0.0 12.7 / 0.0 6.0 / 0.0 7.6 / 0.0 7.8 / 0.0 6.0 / 0.0 7.6 / 0.0 8.1 / 0.0 6.2 / 0.0 9.2 / 0.0 9.7 / 0.0 6.4 / 0.0 11.0 / 0.0 5.2 / 0.0 6.6 / 0.0 6.8 / 0.0 5.6 / 0.0 6.6 / 0.0 7.0 / 0.0 5.8 / 0.0 8.0 / 0.0 8.4 / 0.0 6.0 / 0.0 9.6 / 0.0 4.5 / 0.0 5.6 / 0.0 5.8 / 0.0 4.8 / 0.0 6.2 / 0.0 6.4 / 0.0 5.3 / 0.0 6.8 / 0.0 7.0 / 0.0 5.5 / 0.0 8.4 / 0.0 4.8 / 0.0 5.3 / 0.0 5.5 / 0.0 ns ns ns ns ns ns ns ns ns ns ns iff = input flip-flop or latch * the xc4013xl, xc4036xl, and 4062xl have signi?cantly faster partial and full delay setup times than other devices. notes: input setup time is measured with the fastest route and the lightest load. input hold time is measured using the furthest distance and a reference load of one clock pin per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be used as a worst-case pin-to-pin no-delay input hold speci?cation.
r ds005 (v. 1.8 october 18, 1999 - product speci?cation 6-83 xc4000e and xc4000x series field programmable gate arrays 6 global early clock bufges 1, 2, 5, and 6 set-up and hold for iff and fcl speed grade -3 -2 -1 -09 -08 units description symbol device min min min min min input setup and hold times no delay global early clock and iff global early clock and fcl t psen /t phen t pfsen /t pfhen xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 2.8 / 1.5 1.2 / 4.1 1.2 / 4.4 1.2 / 4.7 1.2 / 4.6 1.2 / 5.3 1.2 / 6.7 1.2 / 6.5 1.2 / 6.7 1.2 / 8.4 1.2 / 8.7 2.5 / 1.3 1.1 / 3.6 1.1 / 3.8 1.1 / 4.1 1.1 / 4.0 1.1 / 4.6 1.1 / 5.8 1.1 / 5.7 1.1 / 5.8 1.1 / 7.3 1.1 / 7.5 2.2 / 1.2 0.9 / 3.1 0.9 / 3.3 0.9 / 3.6 0.9 / 3.5 0.9 / 4.0 0.9 / 5.1 0.9 / 4.9 0.9 / 5.1 0.9 / 6.3 0.9 / 6.6 1.9 / 1.0 0.8 / 2.7 0.8 / 2.9 0.8 / 3.1 0.8 / 3.0 0.8 / 3.5 0.8 / 4.4 0.8 / 4.3 0.8 / 4.4 0.8 / 5.5 0.8 / 5.7 0.5 / 2.7 0.5 / 3.7 0.5 / 4.7 ns ns ns ns ns ns ns ns ns ns ns partial delay global early clock and iff global early clock and fcl t psep /t phep t pfsep /t pfhep xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 8.1 / 0.9 9.0 / 0.0 11.9 / 0.0 6.4 / 0.0 10.8 / 0.0 14.0 / 0.0 7.0 / 0.0 14.6 / 0.0 16.4 / 0.0 9.0 / 0.8 16.7 / 0.0 7.0 / 0.8 8.5 / 0.0 10.4 / 0.0 5.9 / 0.0 10.3 / 0.0 12.2 / 0.0 6.6 / 0.0 12.7 / 0.0 14.3 / 0.0 8.6 / 0.8 14.5 / 0.0 6.1 / 0.7 8.0 / 0.0 9.0 / 0.0 5.4 / 0.0 9.8 / 0.0 10.6 / 0.0 6.2 / 0.0 11.0 / 0.0 12.4 / 0.0 8.2 / 0.8 12.6 / 0.0 5.3 / 0.6 7.5 / 0.0 8.0 / 0.0 4.9 / 0.0 9.0 / 0.0 9.8 / 0.0 5.2 / 0.0 10.8 / 0.0 11.4 / 0.0 7.0 / 0.8 11.6 / 0.0 4.4 / 0.0 4.7 / 0.0 6.3 / 0.5 ns ns ns ns ns ns ns ns ns ns ns full delay global early clock and iff t psed /t phed xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 6.7 / 0.0 10.8 / 0.0 10.3 / 0.0 10.0 / 0.0 12.0 / 0.0 12.6 / 0.0 12.2 / 0.0 13.8 / 0.0 14.1 / 0.0 13.1 / 0.0 17.9 / 0.0 5.8 / 0.0 9.4 / 0.0 9.0 / 0.0 8.7 / 0.0 10.4 / 0.0 11.0 / 0.0 10.6 / 0.0 12.0 / 0.0 12.3 / 0.0 11.4 / 0.0 15.6 / 0.0 5.1 / 0.0 8.2 / 0.0 7.8 / 0.0 7.6 / 0.0 9.1 / 0.0 9.5 / 0.0 9.2 / 0.0 10.5 / 0.0 10.7 / 0.0 9.9 / 0.0 13.6 / 0.0 4.4 / 0.0 7.1 / 0.0 6.8 / 0.0 6.6 / 0.0 7.9 / 0.0 8.3 / 0.0 8.0 / 0.0 9.1 / 0.0 9.3 / 0.0 8.6 / 0.0 11.8 / 0.0 6.0 / 0.0 7.2 / 0.0 7.8 / 0.0 ns ns ns ns ns ns ns ns ns ns ns iff = input flip-flop or latch, fcl = fast capture latch * the xc4013xl, xc4036xl, and 4062xl have signi?cantly faster partial and full delay setup times than other devices. notes: input setup time is measured with the fastest route and the lightest load. input hold time is measured using the furthest distance and a reference load of one clock pin per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be used as a worst-case pin-to-pin no-delay input hold speci?cation.
r xc4000e and xc4000x series field programmable gate arrays 6-84 ds005 (v. 1.8 october 18, 1999 - product speci?cation global early clock bufges 3, 4, 7, and 8 set-up and hold for iff and fcl speed grade -3 -2 -1 -09 -08 units description symbol device min min min min min input setup & hold times no delay global early clock and iff global early clock and fcl t psen /t phen t pfsen /t pfhen xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 3.0 / 2.0 1.2 / 4.1 1.2 / 4.4 1.2 / 4.7 1.2 / 4.6 1.2 / 5.3 1.2 / 6.7 1.2 / 6.5 1.2 / 6.7 1.2 / 8.4 1.2 / 8.7 2.6 / 1.7 1.1 / 3.6 1.1 / 3.8 1.1 / 4.1 1.1 / 4.0 1.1 / 4.6 1.1 / 5.8 1.1 / 5.7 1.1 / 5.8 1.1 / 7.3 1.1 / 7.5 2.3 / 1.5 0.9 / 3.1 0.9 / 3.3 0.9 / 3.6 0.9 / 3.5 0.9 / 4.0 0.9 / 5.1 0.9 / 4.9 0.9 / 5.1 0.9 / 6.3 0.9 / 6.6 2.0 / 1.3 0.8 / 2.7 0.8 / 2.9 0.8 / 3.1 0.8 / 3.0 0.8 / 3.5 0.8 / 4.4 0.8 / 4.3 0.8 / 4.4 0.8 / 5.5 0.8 / 5.7 0.5 / 2.7 0.5 / 3.7 0.5 / 4.7 ns ns ns ns ns ns ns ns ns ns ns partial delay global early clock and iff global early clock and fcl t psep /t phep t pfsep /t pfhep xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 7.3 / 1.5 8.4 / 0.0 10.3 / 0.0 5.4 / 0.0 9.8 / 0.0 12.7 / 0.0 6.4 / 0.8 13.8 / 0.0 14.5 / 0.0 8.4 / 1.5 14.5 / 0.0 6.4 / 1.3 7.9 / 0.0 9.0 / 0.0 4.9 / 0.0 9.3 / 0.0 11.0 / 0.0 5.9 / 0.8 12.0 / 0.0 12.7 / 0.0 7.9 / 1.5 12.7 / 0.0 5.5 / 1.2 7.4 / 0.0 7.8 / 0.0 4.4 / 0.0 8.8 / 0.0 9.6 / 0.0 5.4 / 0.8 10.4 / 0.0 11.0 / 0.0 7.4 / 1.5 11.0 / 0.0 4.8 / 1.0 7.2 / 0.0 7.4 / 0.0 4.3 / 0.0 8.5 / 0.0 9.3 / 0.0 5.0 / 0.8 10.2 / 0.0 10.7 / 0.0 6.8 / 1.5 10.8 / 0.0 4.0 / 0.0 4.6 / 0.2 6.2 / 0.0 ns ns ns ns ns ns ns ns ns ns ns full delay global early clock and iff t psed /t phed xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 5.9 / 0.0 10.8 / 0.0 10.3 / 0.0 10.0 / 0.0 12.0 / 0.0 12.6 / 0.0 12.2 / 0.0 13.8 / 0.0 14.1 / 0.0 13.1 / 0.0 17.9 / 0.0 5.2 / 0.0 9.4 / 0.0 9.0 / 0.0 8.7 / 0.0 10.4 / 0.0 11.0 / 0.0 10.6 / 0.0 12.0 / 0.0 12.3 / 0.0 11.4 / 0.0 15.6 / 0.0 4.5 / 0.0 8.2 / 0.0 7.8 / 0.0 7.6 / 0.0 9.1 / 0.0 9.5 / 0.0 9.2 / 0.0 10.5 / 0.0 10.7 / 0.0 9.9 / 0.0 13.6 / 0.0 3.9 / 0.0 7.1 / 0.0 6.8 / 0.0 6.6 / 0.0 7.9 / 0.0 8.3 / 0.0 8.0 / 0.0 9.1 / 0.0 9.3 / 0.0 8.6 / 0.0 11.8 / 0.0 6.0 / 0.0 7.2 / 0.0 7.8 / 0.0 ns ns ns ns ns ns ns ns ns ns ns * the xc4013xl, xc4036xl, and 4062xl have signi?cantly faster partial and full delay setup times than other devices. iff = input flip flop or latch. fcl = fast capture latch notes: input setup time is measured with the fastest route and the lightest load. input hold time is measured using the furthest distance and a reference load of one clock pin per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be used as a worst-case pin-to-pin no-delay input hold speci?cation.
r ds005 (v. 1.8 october 18, 1999 - product speci?cation 6-85 xc4000e and xc4000x series field programmable gate arrays 6 xc4000xl iob input switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature) . speed grade -3 -2 -1 -09 -08 units description symbol device min min min min min clocks clock enable (ec) to clock (ik) t ecik all devices 0.1 0.1 0.1 0.1 0.1 ns delay from fcl enable (ok) active edge to iff clock (ik) active edge t okik xc4002xl xc4013, 36, 62xl balance of family 3.0 2.2 2.2 2.7 1.9 1.9 2.3 1.6 1.6 2.3 1.6 1.6 1.6 ns ns ns setup times pad to clock (ik), no delay t pick xc4002xl xc4013, 36, 62xl balance of family 2.6 1.7 1.7 2.3 1.5 1.5 2.0 1.3 1.3 2.0 1.3 1.3 1.2 ns ns ns pad to clock (ik), via transparent fast cap- ture latch, no delay t pickf xc4002xl xc4013, 36, 62xl balance of family 3.2 2.3 2.3 2.9 2.0 2.0 2.5 1.8 1.8 2.4 1.7 1.7 1.6 ns ns ns pad to fast capture latch enable (ok), no delay t pock xc4013, 36, 62xl balance of family 1.2 1.2 1.0 1.0 0.9 0.9 0.9 0.9 0.9 ns ns hold times all hold times all devices 0 0 0 0 0 global set/reset minimum gsr pulse width t mrw all devices 19.8 17.3 15.0 14.0 14.0 ns global set/reset max max max max max delay from gsr input to any q t rri* xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 9.8 11.3 13.9 15.9 18.6 20.5 22.5 25.1 27.2 29.1 34.4 8.5 9.8 12.1 13.8 16.1 17.9 19.6 21.9 23.6 25.3 29.9 7.4 8.5 10.5 12.0 14.0 15.5 17.0 19.0 20.5 22.0 26.0 7.0 8.1 10.0 11.4 13.3 14.3 16.2 18.1 19.5 20.9 24.7 10.9 16.2 20.4 ns ns ns ns ns ns ns ns ns ns ns propagation delays pad to i1, i2 t pid all devices 1.6 1.4 1.2 1.1 1.0 ns pad to i1, i2 via transparent input latch, no delay t pli xc4002xl xc4013, 36, 62xl balance of family 4.7 3.1 3.1 4.2 2.7 2.7 3.6 2.4 2.4 3.5 2.2 2.2 2.1 ns ns ns pad to i1, i2 via transparent fcl and in- put latch, no delay t pfli x4002xl xc4013, 36, 62xl balance of family 5.4 3.7 3.7 4.7 3.3 3.3 4.1 2.8 2.8 3.9 2.7 2.7 2.5 ns ns ns clock (ik) to i1, i2 (flip-flop) clock (ik) to i1, i2 (latch enable, active low) fcl enable (ok) active edge to i1, i2 (via transparent standard input latch) t ikri t ikli t okli all devices all devices xc4002xl xc4013, 36, 62xl balance of family 1.7 1.8 5.2 3.6 3.6 1.5 1.6 4.6 3.1 3.1 1.3 1.4 4.0 2.7 2.7 1.2 1.3 3.8 2.6 2.6 1.2 1.3 2.5 ns ns ns ns ns iff = input flip-flop or latch, fcl = fast capture latch * indicates minimum amount of time to assure valid data.
r xc4000e and xc4000x series field programmable gate arrays 6-86 ds005 (v. 1.8 october 18, 1999 - product speci?cation xc4000xl iob output switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation netlist. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). for propagation delays, slew-rate = fast unless otherwise noted. values are expressed in nanoseconds unless otherwise noted. -3 -2 -1 -09 -08 description symbol min max min max min max min max min max clocks clock high clock low t ch t cl 3.0 3.0 2.8 2.8 2.5 2.5 2.3 2.3 2.1 2.1 propagation delays clock (ok) to pad output (o) to pad 3-state to pad hi-z (slew-rate independent) 3-state to pad active and valid output (o) to pad via fast output mux select (ok) to pad via fast mux t okpof t opf t tshz t tsonf t ofpf t okfpf 5.0 4.1 4.0 4.4 5.5 5.1 4.3 3.6 3.5 3.8 4.8 4.5 3.8 3.1 3.0 3.3 4.2 3.9 3.5 3.0 2.9 3.3 4.0 3.7 3.3 2.8 2.9 3.3 3.7 3.4 setup and hold times output (o) to clock (ok) setup time output (o) to clock (ok) hold time clock enable (ec) to clock (ok) setup time clock enable (ec) to clock (ok) hold time t ook t oko t ecok t okec 0.5 0.0 0.0 0.3 0.4 0.0 0.0 0.2 0.3 0.0 0.0 0.1 0.3 0.0 0.0 0.0 0.3 0.0 0.0 0.0 global set/reset minimum gsr pulse width delay from gsr input to any pad xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl t mrw t rpo* 19.8 14.3 15.9 18.5 20.5 23.2 25.1 27.1 29.7 31.7 33.7 39.0 17.3 12.5 13.8 16.1 17.8 20.1 21.9 23.6 25.9 27.6 29.3 33.9 15.0 10.9 12.0 14.0 15.5 17.5 19.0 20.5 22.5 24.0 25.5 29.5 14.0 10.3 11.4 13.3 14.7 16.6 17.6 19.4 21.4 22.8 24.2 28.0 14.0 14.0 19.3 23.5 slew rate adjustment for output slow option add t slow 3.0 2.5 2.0 1.7 1.6 note: output timing is measured at ~50% v cc threshold, with 50 pf external capacitive loads. * indicates minimum amount of time to assure valid data.
r ds005 (v. 1.8 october 18, 1999 - product speci?cation 6-87 xc4000e and xc4000x series field programmable gate arrays 6 revision control version nature of changes 2/1/99 (1.5) release included in the 1999 data book, section 6 5/14/99 (1.6) replaced electrical specification and pinout pages for e, ex, and xl families with separate updates and added url link on placeholder page for electrical specifications/pinouts for weblinx users 9/30/99 (1.7) added power-on specification. 10/18/99 (1.8) corrected posted file to include missing page (iob output parameters).
r xc4000e and xc4000x series field programmable gate arrays 6-88 ds005 (v. 1.8 october 18, 1999 - product speci?cation
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-117 xc4000e and xc4000x series field programmable gate arrays device-speci?c pinout tables device-speci?c tables include all packages for each xc4000 and xc4000x series device. they follow the pad locations around the die, and include boundary scan register locations.. xc4002xl device pinout tables additional xc4002xl package pins ? ? xc4002xl pad names pc84 pq100 vq100 pg120 boundary scan vcc p2 p92 p89 g3 i/o (a8) p3 p93 p90 g1 26 i/o (a9) p4 p94 p91 f1 29 i/o (a10) p5 p97 p94 f3 32 i/o (a11) p6 p98 p95 d1 35 i/o (a12) p7 p99 p96 c1 38 i/o (a13) p8 p100 p97 d2 41 i/o (a14) p9 p1 p98 c2 44 i/o,gck8 (a15) p10 p2 p99 d3 47 vcc p11 p3 p100 c3 gnd p12 p4 p1 c4 i/o, gck1(a16) p13 p5 p2 b2 50 i/o (a17) p14 p6 p3 b3 53 i/o, tdi p15 p7 p4 c5 56 i/o, tck p16 p8 p5 b4 59 i/o, tms p17 p9 p6 b5 62 i/o p18 p10 p7 a4 65 i/o p19 p12 p9 b6 68 i/o p20 p13 p10 a6 71 gnd p21 p14 p11 b7 vcc p22 p15 p12 c7 i/o p23 p16 p13 a7 74 i/o p24 p17 p14 a8 77 i/o p25 p19 p16 c8 80 i/o p26 p20 p17 a10 83 i/o p27 p21 p18 b9 86 i/o - p22 p19 a11 89 i/o p28 p23 p20 c9 92 i/o, gck2 p29 p24 p21 a12 95 o (m1) p30 p25 p22 b11 98 gnd p31 p26 p23 c10 i (m0) p32 p27 p24 c11 101 vcc p33 p28 p25 d11 i (m2) p34 p29 p26 b12 102 i/o, gck3 p35 p30 p27 c12 103 i/o (hdc) p36 p31 p28 a13 106 i/o - p32 p29 d12 109 i/o ( ldc) p37 p33 p30 c13 112 i/o p38 p34 p31 e12 115 i/o p39 p35 p32 d13 118 i/o p40 p38 p35 f12 121 i/o ( init) p41 p39 p36 f13 124 vcc p42 p40 p37 g12 gnd p43 p41 p38 g11 i/o p44 p42 p39 g13 127 i/o p45 p43 p40 h13 130 i/o p46 p46 p43 h11 133 i/o p47 p47 p44 k13 136 i/o p48 p48 p45 j12 139 i/o p49 p49 p46 l13 142 i/o p50 p50 p47 m13 145 i/o, gck4 p51 p51 p48 l12 148 gnd p52 p52 p49 k11 done p53 p53 p50 l11 vcc p54 p54 p51 l10 pr ogram p55 p55 p52 m12 i/o (d7) p56 p56 p53 m11 151 i/o, gck5 p57 p57 p54 n13 154 i/o (d6) p58 p58 p55 m10 157 i/o - p59 p56 n11 160 i/o (d5) p59 p60 p57 m9 163 i/o ( cs0) p60 p61 p58 n10 166 i/o (d4) p61 p64 p61 m8 169 i/o p62 p65 p62 n8 172 vcc p63 p66 p63 m7 gnd p64 p67 p64 l7 i/o (d3) p65 p68 p65 n7 175 i/o ( rs) p66 p69 p66 n6 178 i/o (d2) p67 p71 p68 l6 181 i/o p68 p72 p69 n4 184 i/o (d1) p69 p73 p70 m5 187 i/o ( rclk, rdy/ b usy) p70 p74 p71 n3 190 i/o (d0, din) p71 p75 p72 n2 193 i/o, gck6 (dout) p72 p76 p73 m3 196 cclk p73 p77 p74 l4 vcc p74 p78 p75 l3 o, tdo p75 p79 p76 m2 gnd p76 p80 p77 k3 i/o (a0, ws) p77 p81 p78 l2 2 i/o, gck7(a1) p78 p82 p79 n1 5 i/o (cs1, a2) p79 p83 p80 k2 8 i/o (a3) p80 p84 p81 l1 11 i/o (a4) p81 p85 p82 j2 14 i/o (a5) p82 p86 p83 k1 17 i/o (a6) p83 p89 p86 h2 20 i/o (a7) p84 p90 p87 h1 23 gnd p1 p91 p88 g2 1/22/99 pg120 n.c. pins e1 f2 e2 e3 b1 a1 a2 a3 c6 a5 a9 b8 b10 b13 e11 e13 j13 h12 k12 j11 n12 l9 l8 n9 n5 m6 m4 l5 m1 j3 h3 j1 1/22/99 pq100 n.c. pins p11 p18 p36 p37 p44 p45 p62 p63 p70 p87 p88 p95 p96 1/22//99 vq100 n.c. pins p8 p15 p33 p34 p41 p42 p59 p60 p67 p84 p85 p92 p93 1/22//99 xc4002xl pad names pc84 pq100 vq100 pg120 boundary scan 0
r xc4000e and xc4000x series field programmable gate arrays 6-118 ds006 (v. 1.7) october 4, 1999 - product speci?cation xc4003e device pinout tables additional xc4003e package pins xc4003e pad name pc84 pq100 vq100 pg120 bndry scan vcc p2 p92 p89 g3 - i/o (a8) p3 p93 p90 g1 32 i/o (a9) p4 p94 p91 f1 35 i/o - p95 p92 e1 38 i/o - p96 p93 f2 41 i/o (a10) p5 p97 p94 f3 44 i/o (a11) p6 p98 p95 d1 47 i/o (a12) p7 p99 p96 c1 50 i/o (a13) p8 p100 p97 d2 53 i/o (a14) p9 p1 p98 c2 56 i/o, sgck1 (a15) p10 p2 p99 d3 59 vcc p11 p3 p100 c3 - gnd p12 p4 p1 c4 - i/o, pgck1 (a16) p13 p5 p2 b2 62 i/o (a17) p14 p6 p3 b3 65 i/o, tdi p15 p7 p4 c5 68 i/o, tck p16 p8 p5 b4 71 i/o, tms p17 p9 p6 b5 74 i/o p18 p10 p7 a4 77 i/o - - - c6 80 i/o - p11 p8 a5 83 i/o p19 p12 p9 b6 86 i/o p20 p13 p10 a6 89 gnd p21 p14 p11 b7 - vcc p22 p15 p12 c7 - i/o p23 p16 p13 a7 92 i/o p24 p17 p14 a8 95 i/o - p18 p15 a9 98 i/o - - - b8 101 i/o p25 p19 p16 c8 104 i/o p26 p20 p17 a10 107 i/o p27 p21 p18 b9 110 i/o - p22 p19 a11 113 i/o p28 p23 p20 c9 116 i/o, sgck2 p29 p24 p21 a12 119 o (m1) p30 p25 p22 b11 122 gnd p31 p26 p23 c10 - i (m0) p32 p27 p24 c11 125 vcc p33 p28 p25 d11 - i (m2) p34 p29 p26 b12 126 i/o, pgck2 p35 p30 p27 c12 127 i/o (hdc) p36 p31 p28 a13 130 i/o - p32 p29 d12 133 i/o ( ldc) p37 p33 p30 c13 136 i/o p38 p34 p31 e12 139 i/o p39 p35 p32 d13 142 i/o - p36 p33 f11 145 i/o - p37 p34 e13 148 i/o p40 p38 p35 f12 151 i/o ( init) p41 p39 p36 f13 154 vcc p42 p40 p37 g12 - gnd p43 p41 p38 g11 - i/o p44 p42 p39 g13 157 i/o p45 p43 p40 h13 160 i/o - p44 p41 j13 163 i/o - p45 p42 h12 166 i/o p46 p46 p43 h11 169 i/o p47 p47 p44 k13 172 i/o p48 p48 p45 j12 175 i/o p49 p49 p46 l13 178 i/o p50 p50 p47 m13 181 i/o, sgck3 p51 p51 p48 l12 184 gnd p52 p52 p49 k11 - done p53 p53 p50 l11 - vcc p54 p54 p51 l10 - pr ogram p55 p55 p52 m12 - i/o (d7) p56 p56 p53 m11 187 i/o, pgck3 p57 p57 p54 n13 190 i/o (d6) p58 p58 p55 m10 193 i/o - p59 p56 n11 196 i/o (d5) p59 p60 p57 m9 199 i/o ( cs0) p60 p61 p58 n10 202 i/o - p62 p59 l8 205 i/o - p63 p60 n9 208 i/o (d4) p61 p64 p61 m8 211 i/o p62 p65 p62 n8 214 vcc p63 p66 p63 m7 - gnd p64 p67 p64 l7 - i/o (d3) p65 p68 p65 n7 217 i/o ( rs) p66 p69 p66 n6 220 i/o - p70 p67 n5 223 i/o - - - m6 226 i/o (d2) p67 p71 p68 l6 229 i/o p68 p72 p69 n4 232 i/o (d1) p69 p73 p70 m5 235 i/o ( rclk, rdy/ b usy) p70 p74 p71 n3 238 i/o (d0, din) p71 p75 p72 n2 241 i/o, sgck4 (dout) p72 p76 p73 m3 244 cclk p73 p77 p74 l4 - vcc p74 p78 p75 l3 - o, tdo p75 p79 p76 m2 0 gnd p76 p80 p77 k3 - i/o (a0, ws) p77 p81 p78 l2 2 i/o, pgck4 (a1) p78 p82 p79 n1 5 i/o (cs1, a2) p79 p83 p80 k2 8 i/o (a3) p80 p84 p81 l1 11 i/o (a4) p81 p85 p82 j2 14 i/o (a5) p82 p86 p83 k1 17 i/o - p87 p84 h3 20 i/o - p88 p85 j1 23 i/o (a6) p83 p89 p86 h2 26 i/o (a7) p84 p90 p87 h1 29 gnd p1 p91 p88 g2 - 5/5/97 pg120 not connected pins a1 a2 a3 b1 b10 b13 e2 e3 e11 j3 j11 k12 l5 l9 m1 m4 n12 - 5/5/97 xc4003e pad name pc84 pq100 vq100 pg120 bndry scan
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-119 xc4000e and xc4000x series field programmable gate arrays xc4005e/xl device pnout tables the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc4000 series data sheet for availability information. xc4005e/xl pad name pc 84 pq 100 vq 100?? tq 144 pg 156? pq 160 pq 208 bndry scan vcc p2 p92 p89 p128 h3 p142 p183 - i/o (a8) p3 p93 p90 p129 h1 p143 p184 44 i/o (a9) p4 p94 p91 p130 g1 p144 p185 47 i/o (a19) ?? - p95 p92 p131 g2 p145 p186 50 i/o (a18) ?? - p96 p93 p132 g3 p146 p187 53 i/o (a10) p5 p97 p94 p133 f1 p147 p190 56 i/o (a11) p6 p98 p95 p134 f2 p148 p191 59 i/o - - - p135 e1 p149 p192 62 i/o - - - p136 e2 p150 p193 65 gnd - - - p137 f3 p151 p194 - i/o (a12) p7 p99 p96 p138 e3 p154 p199 68 i/o (a13) p8 p100 p97 p139 c1 p155 p200 71 i/o - - - p140 c2 p156 p201 74 i/o - - - p141 d3 p157 p202 77 i/o (a14) p9 p1 p98 p142 b1 p158 p203 80 i/o, sgck1 ?, gck8 ?? (a15) p10 p2 p99 p143 b2 p159 p204 83 vcc p11 p3 p100 p144 c3 p160 p205 - gnd p12 p4 p1 p1 c4 p1 p2 - i/o, pgck1?, gck1?? (a16) p13 p5 p2 p2 b3 p2 p4 86 i/o (a17) p14 p6 p3 p3 a1 p3 p5 89 i/o - - - p4a2p4p692 i/o - - - p5 c5 p5 p7 95 i/o, tdi p15 p7 p4 p6 b4 p6 p8 98 i/o, tck p16 p8 p5 p7 a3 p7 p9 101 gnd - - - p8 c6 p10 p14 - i/o - - - p9 b5 p11 p15 104 i/o - - - p10 b6 p12 p16 107 i/o, tms p17 p9 p6 p11 a5 p13 p17 110 i/o p18 p10 p7 p12 c7 p14 p18 113 i/o - - - p13 b7 p15 p21 116 i/o - p11 p8 p14 a6 p16 p22 119 i/o p19 p12 p9 p15 a7 p17 p23 122 i/o p20 p13 p10 p16 a8 p18 p24 125 gnd p21 p14 p11 p17 c8 p19 p25 - vcc p22 p15 p12 p18 b8 p20 p26 - i/o p23 p16 p13 p19 c9 p21 p27 128 i/o p24 p17 p14 p20 b9 p22 p28 131 i/o - p18 p15 p21 a9 p23 p29 134 i/o - - - p22 b10 p24 p30 137 i/o p25 p19 p16 p23 c10 p25 p33 140 i/o p26 p20 p17 p24 a10 p26 p34 143 i/o - - - p25 a11 p27 p35 146 i/o - - - p26 b11 p28 p36 149 gnd - - - p27 c11 p29 p37 - i/o p27 p21 p18 p28 b12 p32 p42 152 i/o - p22 p19 p29 a13 p33 p43 155 i/o - - - p30 a14 p34 p44 158 i/o - - - p31 c12 p35 p45 161 i/o p28 p23 p20 p32 b13 p36 p46 164 i/o, sgck2 ?, gck2 ?? p29 p24 p21 p33 b14 p37 p47 167 o (m1) p30 p25 p22 p34 a15 p38 p48 170 gnd p31 p26 p23 p35 c13 p39 p49 - i (m0) p32 p27 p24 p36 a16 p40 p50 173 vcc p33 p28 p25 p37 c14 p41 p55 - i (m2) p34 p29 p26 p38 b15 p42 p56 174 i/o, pgck2 ?, gck3 ?? p35 p30 p27 p39 b16 p43 p57 175 i/o (hdc) p36 p31 p28 p40 d14 p44 p58 178 i/o - - - p41 c15 p45 p59 181 i/o - - - p42 d15 p46 p60 184 i/o - p32 p29 p43 e14 p47 p61 187 i/o ( ldc) p37 p33 p30 p44 c16 p48 p62 190 gnd - - - p45 f14 p51 p67 - i/o - - - p46 f15 p52 p68 193 i/o - - - p47 e16 p53 p69 196 i/o p38 p34 p31 p48 f16 p54 p70 199 i/o p39 p35 p32 p49 g14 p55 p71 202 i/o - p36 p33 p50 g15 p56 p74 205 i/o - p37 p34 p51 g16 p57 p75 208 i/o p40 p38 p35 p52 h16 p58 p76 211 i/o ( init) p41 p39 p36 p53 h15 p59 p77 214 vcc p42 p40 p37 p54 h14 p60 p78 - gnd p43 p41 p38 p55 j14 p61 p79 - i/o p44 p42 p39 p56 j15 p62 p80 217 i/o p45 p43 p40 p57 j16 p63 p81 220 i/o - p44 p41 p58 k16 p64 p82 223 i/o - p45 p42 p59 k15 p65 p83 226 i/o p46 p46 p43 p60 k14 p66 p86 229 i/o p47 p47 p44 p61 l16 p67 p87 232 i/o - - - p62 m16 p68 p88 235 i/o - - - p63 l15 p69 p89 238 gnd - - - p64 l14 p70 p90 - i/o p48 p48 p45 p65 p16 p73 p95 241 i/o p49 p49 p46 p66 m14 p74 p96 244 i/o - - - p67 n15 p75 p97 247 i/o - - - p68 p15 p76 p98 250 i/o p50 p50 p47 p69 n14 p77 p99 253 i/o, sgck3 ?, gck4 ?? p51 p51 p48 p70 r16 p78 p100 256 gnd p52 p52 p49 p71 p14 p79 p101 - done p53 p53 p50 p72 r15 p80 p103 - vcc p54 p54 p51 p73 p13 p81 p106 - pr ogram p55 p55 p52 p74 r14 p82 p108 - i/o (d7) p56 p56 p53 p75 t16 p83 p109 259 i/o, pgck3?, gck5?? p57 p57 p54 p76 t15 p84 p110 262 i/o - - - p77 r13 p85 p111 265 i/o - - - p78 p12 p86 p112 268 i/o (d6) p58 p58 p55 p79 t14 p87 p113 271 i/o - p59 p56 p80 t13 p88 p114 274 gnd - - - p81 p11 p91 p119 - i/o - - - p82 r11 p92 p120 277 i/o - - - p83 t11 p93 p121 280 i/o (d5) p59 p60 p57 p84 t10 p94 p122 283 i/o ( cs0) p60 p61 p58 p85 p10 p95 p123 286 i/o - p62 p59 p86 r10 p96 p126 289 i/o - p63 p60 p87 t9 p97 p127 292 i/o (d4) p61 p64 p61 p88 r9 p98 p128 295 i/o p62 p65 p62 p89 p9 p99 p129 298 vcc p63 p66 p63 p90 r8 p100 p130 - gnd p64 p67 p64 p91 p8 p101 p131 - i/o (d3) p65 p68 p65 p92 t8 p102 p132 301 i/o ( rs) p66 p69 p66 p93 t7 p103 p133 304 i/o - p70 p67 p94 t6 p104 p134 307 i/o - - - p95 r7 p105 p135 310 i/o (d2) p67 p71 p68 p96 p7 p106 p138 313 i/o p68 p72 p69 p97 t5 p107 p139 316 i/o - - - p98 r6 p108 p140 319 i/o - - - p99 t4 p109 p141 322 gnd - - - p100 p6 p110 p142 - i/o (d1) p69 p73 p70 p101 t3 p113 p147 325 i/o ( rclk, rdy/ b usy) p70 p74 p71 p102 p5 p114 p148 328 i/o - - - p103 r4 p115 p149 331 i/o - - - p104 r3 p116 p150 334 i/o (d0, din) p71 p75 p72 p105 p4 p117 p151 337 xc4005e/xl pad name pc 84 pq 100 vq 100?? tq 144 pg 156? pq 160 pq 208 bndry scan
r xc4000e and xc4000x series field programmable gate arrays 6-120 ds006 (v. 1.7) october 4, 1999 - product speci?cation ? = e only ?? = xl only additional xc4005e/xl package pins xc4006e device pinout tables i/o, sgck4 ?, gck6 ?? (dout) p72 p76 p73 p106 t2 p118 p152 340 cclk p73 p77 p74 p107 r2 p119 p153 - vcc p74 p78 p75 p108 p3 p120 p154 - o, tdo p75 p79 p76 p109 t1 p121 p159 0 gnd p76 p80 p77 p110 n3 p122 p160 - i/o (a0, ws) p77 p81 p78 p111 r1 p123 p161 2 i/o, pgck4 ?, gck7 ?? (a1) p78 p82 p79 p112 p2 p124 p162 5 i/o - - - p113 n2 p125 p163 8 i/o - - - p114 m3 p126 p164 11 i/o (cs1, a2) p79 p83 p80 p115 p1 p127 p165 14 i/o (a3) p80 p84 p81 p116 n1 p128 p166 17 gnd - - - p118 l3 p131 p171 - i/o - - - p119 l2 p132 p172 20 i/o - - - p120 l1 p133 p173 23 i/o (a4) p81 p85 p82 p121 k3 p134 p174 26 i/o (a5) p82 p86 p83 p122 k2 p135 p175 29 i/o (a21) ?? - p87 p84 p123 k1 p137 p178 32 i/o (a20) ?? - p88 p85 p124 j1 p138 p179 35 i/o (a6) p83 p89 p86 p125 j2 p139 p180 38 i/o (a7) p84 p90 p87 p126 j3 p140 p181 41 gnd p1 p91 p88 p127 h2 p141 p182 - 6/10/97 tq144 not connected pins p117 - - - - - 5/5/97 xc4005e/xl pad name pc 84 pq 100 vq 100?? tq 144 pg 156? pq 160 pq 208 bndry scan pg156 not connected pins a4 a12 d1 d2 d16 e15 m1 m2 m15 n16 r5 r12 t12 - - - - - 5/5/97 pq160 not connected pins p8 p9 p30 p31 p49 p50 p71 p72 p89 p90 p111 p112 p129 p130 p136 p152 p153 - 6/16/97 pq208 not connected pins p1 p3 p10 p11 p12 p13 p19 p20 p31 p32 p38 p39 p40 p41 p51 p52 p53 p54 p63 p64 p65 p66 p72 p73 p84 p85 p91 p92 p93 p94 p102 p104 p105 p107 p115 p116 p117 p118 p124 p125 p136 p137 p143 p144 p145 p146 p155 p156 p157 p158 p167 p168 p169 p170 p176 p177 p188 p189 p195 p196 p197 p198 p206 p207 p208 - 6/5/97 xc4006e pad name pc 84 tq 144 pg 156 pq 160 pq 208 bndry scan vcc p2 p128 h3 p142 p183 - i/o (a8) p3 p129 h1 p143 p184 50 i/o (a9) p4 p130 g1 p144 p185 53 i/o - p131 g2 p145 p186 56 i/o - p132 g3 p146 p187 59 i/o (a10) p5 p133 f1 p147 p190 62 i/o (a11) p6 p134 f2 p148 p191 65 i/o - p135 e1 p149 p192 68 i/o - p136 e2 p150 p193 71 gnd - p137 f3 p151 p194 - i/o - - d1 p152 p197 74 i/o - - d2 p153 p198 77 i/o (a12) p7 p138 e3 p154 p199 80 i/o (a13) p8 p139 c1 p155 p200 83 i/o - p140 c2 p156 p201 86 i/o - p141 d3 p157 p202 89 i/o (a14) p9 p142 b1 p158 p203 92 i/o, sgck1 (a15) p10 p143 b2 p159 p204 95 vcc p11 p144 c3 p160 p205 - gnd p12 p1 c4 p1 p2 - i/o, pgck1 (a16) p13 p2 b3 p2 p4 98 i/o (a17) p14 p3 a1 p3 p5 101 i/o - p4 a2 p4 p6 104 i/o - p5 c5 p5 p7 107 i/o, tdi p15 p6 b4 p6 p8 110 i/o, tck p16 p7 a3 p7 p9 113 i/o - - a4 p8 p10 116 i/o - - - p9 p11 119 gnd - p8 c6 p10 p14 - i/o - p9 b5 p11 p15 122 i/o - p10 b6 p12 p16 125 i/o, tms p17 p11 a5 p13 p17 128 i/o p18 p12 c7 p14 p18 131 i/o - p13 b7 p15 p21 134 i/o - p14 a6 p16 p22 137 i/o p19 p15 a7 p17 p23 140 i/o p20 p16 a8 p18 p24 143 gnd p21 p17 c8 p19 p25 - vcc p22 p18 b8 p20 p26 - i/o p23 p19 c9 p21 p27 146 i/o p24 p20 b9 p22 p28 149 i/o - p21 a9 p23 p29 152 i/o - p22 b10 p24 p30 155 i/o p25 p23 c10 p25 p33 158 i/o p26 p24 a10 p26 p34 161 i/o - p25 a11 p27 p35 164 i/o - p26 b11 p28 p36 167 gnd - p27 c11 p29 p37 - i/o - - a12 p30 p40 170 i/o - - - p31 p41 173 i/o p27 p28 b12 p32 p42 176 i/o - p29 a13 p33 p43 179 i/o - p30 a14 p34 p44 182 i/o - p31 c12 p35 p45 185 i/o p28 p32 b13 p36 p46 188 i/o, sgck2 p29 p33 b14 p37 p47 191 o (m1) p30 p34 a15 p38 p48 194 gnd p31 p35 c13 p39 p49 - xc4006e pad name pc 84 tq 144 pg 156 pq 160 pq 208 bndry scan
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-121 xc4000e and xc4000x series field programmable gate arrays additional xc4006e package pins i (m0) p32 p36 a16 p40 p50 197 vcc p33 p37 c14 p41 p55 - i (m2) p34 p38 b15 p42 p56 198 i/o, pgck2 p35 p39 b16 p43 p57 199 i/o (hdc) p36 p40 d14 p44 p58 202 i/o - p41 c15 p45 p59 205 i/o - p42 d15 p46 p60 208 i/o - p43 e14 p47 p61 211 i/o ( ldc) p37 p44 c16 p48 p62 214 i/o - - e15 p49 p63 217 i/o - - d16 p50 p64 220 gnd - p45 f14 p51 p67 - i/o - p46 f15 p52 p68 223 i/o - p47 e16 p53 p69 226 i/o p38 p48 f16 p54 p70 229 i/o p39 p49 g14 p55 p71 232 i/o - p50 g15 p56 p74 235 i/o - p51 g16 p57 p75 238 i/o p40 p52 h16 p58 p76 241 i/o ( init) p41 p53 h15 p59 p77 244 vcc p42 p54 h14 p60 p78 - gnd p43 p55 j14 p61 p79 - i/o p44 p56 j15 p62 p80 247 i/o p45 p57 j16 p63 p81 250 i/o - p58 k16 p64 p82 253 i/o - p59 k15 p65 p83 256 i/o p46 p60 k14 p66 p86 259 i/o p47 p61 l16 p67 p87 262 i/o - p62 m16 p68 p88 265 i/o - p63 l15 p69 p89 268 gnd - p64 l14 p70 p90 - i/o - - n16 p71 p93 271 i/o - - m15 p72 p94 274 i/o p48 p65 p16 p73 p95 277 i/o p49 p66 m14 p74 p96 280 i/o - p67 n15 p75 p97 283 i/o - p68 p15 p76 p98 286 i/o p50 p69 n14 p77 p99 289 i/o, sgck3 p51 p70 r16 p78 p100 292 gnd p52 p71 p14 p79 p101 - done p53 p72 r15 p80 p103 - vcc p54 p73 p13 p81 p106 - pr ogram p55 p74 r14 p82 p108 - i/o (d7) p56 p75 t16 p83 p109 295 i/o, pgck3 p57 p76 t15 p84 p110 298 i/o - p77 r13 p85 p111 301 i/o - p78 p12 p86 p112 304 i/o (d6) p58 p79 t14 p87 p113 307 i/o - p80 t13 p88 p114 310 i/o - - r12 p89 p115 313 i/o - - t12 p90 p116 316 gnd - p81 p11 p91 p119 - i/o - p82 r11 p92 p120 319 i/o - p83 t11 p93 p121 322 i/o (d5) p59 p84 t10 p94 p122 325 i/o ( cs0) p60 p85 p10 p95 p123 328 i/o - p86 r10 p96 p126 331 i/o - p87 t9 p97 p127 334 i/o (d4) p61 p88 r9 p98 p128 337 i/o p62 p89 p9 p99 p129 340 vcc p63 p90 r8 p100 p130 - gnd p64 p91 p8 p101 p131 - i/o (d3) p65 p92 t8 p102 p132 343 i/o ( rs) p66 p93 t7 p103 p133 346 xc4006e pad name pc 84 tq 144 pg 156 pq 160 pq 208 bndry scan i/o - p94 t6 p104 p134 349 i/o - p95 r7 p105 p135 352 i/o (d2) p67 p96 p7 p106 p138 355 i/o p68 p97 t5 p107 p139 358 i/o - p98 r6 p108 p140 361 i/o - p99 t4 p109 p141 364 gnd - p100 p6 p110 p142 - i/o - - r5 p111 p145 367 i/o - - - p112 p146 370 i/o (d1) p69 p101 t3 p113 p147 373 i/o ( rclk, rdy/ b usy) p70 p102 p5 p114 p148 376 i/o - p103 r4 p115 p149 379 i/o - p104 r3 p116 p150 382 i/o (d0, din) p71 p105 p4 p117 p151 385 i/o, sgck4 (dout) p72 p106 t2 p118 p152 388 cclk p73 p107 r2 p119 p153 - vcc p74 p108 p3 p120 p154 - o, tdo p75 p109 t1 p121 p159 0 gnd p76 p110 n3 p122 p160 - i/o (a0, ws) p77 p111 r1 p123 p161 2 i/o, pgck4 (a1) p78 p112 p2 p124 p162 5 i/o - p113 n2 p125 p163 8 i/o - p114 m3 p126 p164 11 i/o (cs1, a2) p79 p115 p1 p127 p165 14 i/o (a3) p80 p116 n1 p128 p166 17 i/o - p117 m2 p129 p167 20 i/o - - m1 p130 p168 23 gnd - p118 l3 p131 p171 - i/o - p119 l2 p132 p172 26 i/o - p120 l1 p133 p173 29 i/o (a4) p81 p121 k3 p134 p174 32 i/o (a5) p82 p122 k2 p135 p175 35 i/o - p123 k1 p137 p178 38 i/o - p124 j1 p138 p179 41 i/o (a6) p83 p125 j2 p139 p180 44 i/o (a7) p84 p126 j3 p140 p181 47 gnd p1 p127 h2 p141 p182 - 5/5/97 pq160 not connected pins p136 ---- 5/5/97 pq208 not connected pins p1 p3 p12 p13 p19 p20 p31 p32 p38 p39 p51 p52 p53 p54 p65 p66 p72 p73 p84 p85 p91 p92 p102 p104 p105 p107 p117 p118 p124 p125 p136 p137 p143 p144 p155 p156 p157 p158 p169 p170 p176 p177 p188 p189 p195 p196 p206 p207 p208 - 6/5/97 xc4006e pad name pc 84 tq 144 pg 156 pq 160 pq 208 bndry scan
r xc4000e and xc4000x series field programmable gate arrays 6-122 ds006 (v. 1.7) october 4, 1999 - product speci?cation xc4008e device pinout tables xc4008e pad name pc84 pq160 pg191 pq208 bndry scan vcc p2 p142 j4 p183 - i/o (a8) p3 p143 j3 p184 56 i/o (a9) p4 p144 j2 p185 59 i/o - p145 j1 p186 62 i/o - p146 h1 p187 65 i/o - - h2 p188 68 i/o - - h3 p189 71 i/o (a10) p5 p147 g1 p190 74 i/o (a11) p6 p148 g2 p191 77 i/o - p149 f1 p192 80 i/o - p150 e1 p193 83 gnd - p151 g3 p194 - i/o - p152 c1 p197 86 i/o - p153 e2 p198 89 i/o (a12) p7 p154 f3 p199 92 i/o (a13) p8 p155 d2 p200 95 i/o - p156 b1 p201 98 i/o - p157 e3 p202 101 i/o (a14) p9 p158 c2 p203 104 i/o, sgck1 (a15) p10 p159 b2 p204 107 vcc p11 p160 d3 p205 - gnd p12 p1 d4 p2 - i/o, pgck1 (a16) p13 p2 c3 p4 110 i/o (a17) p14 p3 c4 p5 113 i/o - p4 b3 p6 116 i/o - p5 c5 p7 119 i/o, tdi p15 p6 a2 p8 122 i/o, tck p16 p7 b4 p9 125 i/o - p8 c6 p10 128 i/o - p9 a3 p11 131 gnd - p10 c7 p14 - i/o - p11 a4 p15 134 i/o - p12 a5 p16 137 i/o, tms p17 p13 b7 p17 140 i/o p18 p14 a6 p18 143 i/o - - c8 p19 146 i/o - - a7 p20 149 i/o - p15 b8 p21 152 i/o - p16 a8 p22 155 i/o p19 p17 b9 p23 158 i/o p20 p18 c9 p24 161 gnd p21 p19 d9 p25 - vcc p22 p20 d10 p26 - i/o p23 p21 c10 p27 164 i/o p24 p22 b10 p28 167 i/o - p23 a9 p29 170 i/o - p24 a10 p30 173 i/o - - a11 p31 176 i/o - - c11 p32 179 i/o p25 p25 b11 p33 182 i/o p26 p26 a12 p34 185 i/o - p27 b12 p35 188 i/o - p28 a13 p36 191 gnd - p29 c12 p37 - i/o - p30 a15 p40 194 i/o - p31 c13 p41 197 i/o p27 p32 b14 p42 200 i/o - p33 a16 p43 203 i/o - p34 b15 p44 206 i/o - p35 c14 p45 209 i/o p28 p36 a17 p46 212 i/o, sgck2 p29 p37 b16 p47 215 o (m1) p30 p38 c15 p48 218 gnd p31 p39 d15 p49 - i (m0) p32 p40 a18 p50 221 vcc p33 p41 d16 p55 - i (m2) p34 p42 c16 p56 222 i/o, pgck2 p35 p43 b17 p57 223 i/o (hdc) p36 p44 e16 p58 226 i/o - p45 c17 p59 229 i/o - p46 d17 p60 232 i/o - p47 b18 p61 235 i/o ( ldc) p37 p48 e17 p62 238 i/o - p49 f16 p63 241 i/o - p50 c18 p64 244 gnd - p51 g16 p67 - i/o - p52 e18 p68 247 i/o - p53 f18 p69 250 i/o p38 p54 g17 p70 253 i/o p39 p55 g18 p71 256 i/o - - h16 p72 259 i/o - - h17 p73 262 i/o - p56 h18 p74 265 i/o - p57 j18 p75 268 i/o p40 p58 j17 p76 271 i/o ( init) p41 p59 j16 p77 274 vcc p42 p60 j15 p78 - gnd p43 p61 k15 p79 - i/o p44 p62 k16 p80 277 i/o p45 p63 k17 p81 280 i/o - p64 k18 p82 283 i/o - p65 l18 p83 286 i/o - - l17 p84 289 i/o - - l16 p85 292 i/o p46 p66 m18 p86 295 i/o p47 p67 m17 p87 298 i/o - p68 n18 p88 301 i/o - p69 p18 p89 304 gnd - p70 m16 p90 - i/o - p71 t18 p93 307 i/o - p72 p17 p94 310 i/o p48 p73 n16 p95 313 i/o p49 p74 t17 p96 316 i/o - p75 r17 p97 319 i/o - p76 p16 p98 322 i/o p50 p77 u18 p99 325 i/o, sgck3 p51 p78 t16 p100 328 gnd p52 p79 r16 p101 - done p53 p80 u17 p103 - vcc p54 p81 r15 p106 - pr ogram p55 p82 v18 p108 - i/o (d7) p56 p83 t15 p109 331 i/o, pgck3 p57 p84 u16 p110 334 i/o - p85 t14 p111 337 i/o - p86 u15 p112 340 i/o (d6) p58 p87 v17 p113 343 i/o - p88 v16 p114 346 i/o - p89 t13 p115 349 i/o - p90 u14 p116 352 gnd - p91 t12 p119 - i/o - p92 u13 p120 355 i/o - p93 v13 p121 358 i/o (d5) p59 p94 u12 p122 361 i/o ( cs0) p60 p95 v12 p123 364 i/o - - t11 p124 367 i/o - - u11 p125 370 i/o - p96 v11 p126 373 i/o - p97 v10 p127 376 i/o (d4) p61 p98 u10 p128 379 i/o p62 p99 t10 p129 382 vcc p63 p100 r10 p130 - gnd p64 p101 r9 p131 - i/o (d3) p65 p102 t9 p132 385 i/o ( rs) p66 p103 u9 p133 388 i/o - p104 v9 p134 391 i/o - p105 v8 p135 394 i/o - - u8 p136 397 xc4008e pad name pc84 pq160 pg191 pq208 bndry scan
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-123 xc4000e and xc4000x series field programmable gate arrays additional xc4008e package pins i/o - - t8 p137 400 i/o (d2) p67 p106 v7 p138 403 i/o p68 p107 u7 p139 406 i/o - p108 v6 p140 409 i/o - p109 u6 p141 412 gnd - p110 t7 p142 - i/o - p111 u5 p145 415 i/o - p112 t6 p146 418 i/o (d1) p69 p113 v3 p147 421 i/o ( rclk, rdy/ b usy) p70 p114 v2 p148 424 i/o - p115 u4 p149 427 i/o - p116 t5 p150 430 i/o (d0, din) p71 p117 u3 p151 433 i/o, sgck4 (dout) p72 p118 t4 p152 436 cclk p73 p119 v1 p153 - vcc p74 p120 r4 p154 - o, tdo p75 p121 u2 p159 0 gnd p76 p122 r3 p160 - i/o (a0, ws) p77 p123 t3 p161 2 i/o, pgck4 (a1) p78 p124 u1 p162 5 i/o - p125 p3 p163 8 i/o - p126 r2 p164 11 i/o (cs1, a2) p79 p127 t2 p165 14 i/o (a3) p80 p128 n3 p166 17 i/o - p129 p2 p167 20 i/o - p130 t1 p168 23 gnd - p131 m3 p171 - i/o - p132 p1 p172 26 i/o - p133 n1 p173 29 xc4008e pad name pc84 pq160 pg191 pq208 bndry scan i/o (a4) p81 p134 m2 p174 32 i/o (a5) p82 p135 m1 p175 35 i/o - - l3 p176 38 i/o - p136 l2 p177 41 i/o - p137 l1 p178 44 i/o - p138 k1 p179 47 i/o (a6) p83 p139 k2 p180 50 i/o (a7) p84 p140 k3 p181 53 gnd p1 p141 k4 p182 - 5/5/97 pg191 not connected pins a14 b5 b6 b13 d1 d18 f2 f17 n2 n17 r1 r18 v4 v5 v14 v15 - - 6/3/97 pq208 not connected pins p1 p3 p12 p13 p38 p39 p51 p52 p53 p54 p65 p66 p91 p92 p102 p104 p105 p107 p117 p118 p143 p144 p155 p156 p157 p158 p169 p170 p195 p196 p206 p207 p208 - - - xc4008e pad name pc84 pq160 pg191 pq208 bndry scan
r xc4000e and xc4000x series field programmable gate arrays 6-124 ds006 (v. 1.7) october 4, 1999 - product speci?cation xc4010e/xl device pinout tables the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc4000 series data sheet for availability information. xc4010e/xl pad name pc 84 pq 100?? tq 144?? pq 160 tq 176?? pg 191? pq/h q 208 bg 225? bg 256?? bndry scan vcc p2 p92 p128 p142 p155 vcc* p183 vcc* vcc* - i/o (a8) p3 p93 p129 p143 p156 j3 p184 e8 c10 62 i/o (a9) p4 p94 p130 p144 p157 j2 p185 b7 d10 65 i/o (19) - p95 p131 p145 p158 j1 p186 a7 a9 68 i/o (18) - p96 p132 p146 p159 h1 p187 c7 b9 71 i/o - - - - p160 h2 p188 d7 c9 74 i/o - - - - p161 h3 p189 e7 d9 77 i/o (a10) p5 p97 p133 p147 p162 g1 p190 a6 a8 80 i/o (a11) p6 p98 p134 p148 p163 g2 p191 b6 b8 83 vcc - - - - - vcc* - vcc* vcc* - i/o - - p135 p149 p164 f1 p192 a5 b6 86 i/o - - p136 p150 p165 e1 p193 b5 a5 89 gnd - - p137 p151 p166 gnd* p194 gnd* gnd* - i/o - - - - - f2 p195 d6 c6 92 i/o - - - - p167 d1 p196 c5 b5 95 i/o - - - p152 p168 c1 p197 a4 a4 98 i/o - - - p153 p169 e2 p198 e6 c5 101 i/o (a12) p7 p99 p138 p154 p170 f3 p199 b4 b4 104 i/o (a13) p8 p100 p139 p155 p171 d2 p200 d5 a3 107 i/o - - p140 p156 p172 b1 p201 b3 b3 110 i/o - - p141 p157 p173 e3 p202 f6 b2 113 i/o (a14) p9 p1 p142 p158 p174 c2 p203 a2 a2 116 i/o, sgck1 ?, gck8 ?? (a15) p10 p2 p143 p159 p175 b2 p204 c3 c3 119 vcc p11 p3 p144 p160 p176 vcc* p205 vcc* vcc* - gnd p12 p4 p1 p1 p1 gnd* p2 gnd* gnd* - i/o, pgck1?, gck1?? (a16) p13 p5 p2 p2 p2 c3 p4 d4 b1 122 i/o (a17) p14 p6 p3 p3 p3 c4 p5 b1 c2 125 i/o - - p4 p4 p4 b3 p6 c2 d2 128 i/o - - p5 p5 p5 c5 p7 e5 d3 131 i/o, tdi p15 p7 p6 p6 p6 a2 p8 d3 e4 134 i/o, tck p16 p8 p7 p7 p7 b4 p9 c1 c1 137 i/o - - - p8 p8 c6 p10 d2 d1 140 i/o - - - p9 p9 a3 p11 g6 e3 143 i/o - - - - - b5 p12 e4 e2 146 i/o - - - - - b6 p13 d1 e1 149 gnd - - p8 p10 p10 gnd* p14 gnd* gnd* - i/o - - p9 p11 p11 a4 p15 f5 g3 152 i/o - - p10 p12 p12 a5 p16 e1 g2 155 i/o, tms p17 p9 p11 p13 p13 b7 p17 f4 g1 158 i/o p18 p10 p12 p14 p14 a6 p18 f3 h3 161 vcc - - - - - vcc* - vcc* vcc* - i/o - - - - p15 c8 p19 g4 j2 164 i/o - - - - p16 a7 p20 g3 j1 167 i/o - - p13 p15 p17 b8 p21 g2 k2 170 i/o - p11 p14 p16 p18 a8 p22 g1 k3 173 i/o p19 p12 p15 p17 p19 b9 p23 g5 k1 176 i/o p20 p13 p16 p18 p20 c9 p24 h3 l1 179 gnd p21 p14 p17 p19 p21 gnd* p25 gnd* gnd* - vcc p22 p15 p18 p20 p22 vcc* p26 vcc* vcc* - i/o p23 p16 p19 p21 p23 c10 p27 h4 l2 182 i/o p24 p17 p20 p22 p24 b10 p28 h5 l3 185 i/o - p18 p21 p23 p25 a9 p29 j2 l4 188 i/o - - p22 p24 p26 a10 p30 j1 m1 191 i/o - - - - p27 a11 p31 j3 m2 194 i/o - - - - p28 c11 p32 j4 m3 197 vcc - - - - - vcc* - vcc* vcc* - i/o p25 p19 p23 p25 p29 b11 p33 k2 p1 200 i/o p26 p20 p24 p26 p30 a12 p34 k3 p2 203 i/o - - p25 p27 p31 b12 p35 j6 r1 206 i/o - - p26 p28 p32 a13 p36 l1 p3 209 gnd - - p27 p29 p33 gnd* p37 gnd* gnd* - i/o - - - - - b13 p38 l3 t2 212 i/o - - - - - a14 p39 m1 u1 215 i/o - - - p30 p34 a15 p40 k5 t3 218 i/o - - - p31 p35 c13 p41 m2 u2 221 i/o p27 p21 p28 p32 p36 b14 p42 l4 v1 224 i/o - p22 p29 p33 p37 a16 p43 n1 t4 227 i/o - - p30 p34 p38 b15 p44 m3 u3 230 i/o - - p31 p35 p39 c14 p45 n2 v2 233 i/o p28 p23 p32 p36 p40 a17 p46 k6 w1 236 i/o, sgck2 ?, gck2 ?? p29 p24 p33 p37 p41 b16 p47 p1 v3 239 o (m1) p30 p25 p34 p38 p42 c15 p48 n3 w2 242 gnd p31 p26 p35 p39 p43 gnd* p49 gnd* gnd* - i (m0) p32 p27 p36 p40 p44 a18 p50 p2 y1 245 vcc p33 p28 p37 p41 p45 vcc* p55 vcc* vcc* - i (m2) p34 p29 p38 p42 p46 c16 p56 m4 w3 246 i/o, pgck2 ?, gck3 ?? p35 p30 p39 p43 p47 b17 p57 r2 y2 247 i/o (hdc) p36 p31 p40 p44 p48 e16 p58 p3 w4 250 i/o - - p41 p45 p49 c17 p59 l5 v4 253 i/o - - p42 p46 p50 d17 p60 n4 u5 256 i/o - p32 p43 p47 p51 b18 p61 r3 y3 259 i/o ( ldc) p37 p33 p44 p48 p52 e17 p62 p4 y4 262 i/o - - - p49 p53 f16 p63 k7 v5 265 i/o - - - p50 p54 c18 p64 m5 w5 268 i/o - - - - - d18 p65 r4 y5 271 i/o - - - - - f17 p66 n5 v6 274 gnd - - p45 p51 p55 gnd* p67 gnd* gnd* - i/o - - p46 p52 p56 e18 p68 r5 w7 277 i/o - - p47 p53 p57 f18 p69 m6 y7 280 i/o p38 p34 p48 p54 p58 g17 p70 n6 v8 283 i/o p39 p35 p49 p55 p59 g18 p71 p6 w8 286 vcc - - - - - vcc* - vcc* vcc* - i/o - - - - p60 h16 p72 r6 y8 289 i/o - - - - p61 h17 p73 m7 u9 292 i/o - p36 p50 p56 p62 h18 p74 r7 v10 295 i/o - p37 p51 p57 p63 j18 p75 l7 y10 298 i/o p40 p38 p52 p58 p64 j17 p76 n8 y11 301 i/o ( init) p41 p39 p53 p59 p65 j16 p77 p8 w11 304 vcc p42 p40 p54 p60 p66 vcc* p78 vcc* vcc* - gnd p43 p41 p55 p61 p67 gnd* p79 gnd* gnd* - i/o p44 p42 p56 p62 p68 k16 p80 l8 v11 307 i/o p45 p43 p57 p63 p69 k17 p81 p9 u11 310 i/o - p44 p58 p64 p70 k18 p82 r9 y12 313 i/o - p45 p59 p65 p71 l18 p83 n9 w12 316 i/o - - - - p72 l17 p84 m9 v12 319 i/o - - - - p73 l16 p85 l9 u12 322 vcc - - - - - vcc* - vcc* vcc* - i/o p46 p46 p60 p66 p74 m18 p86 n10 y15 325 i/o p47 p47 p61 p67 p75 m17 p87 k9 v14 328 i/o - - p62 p68 p76 n18 p88 r11 w15 331 i/o - - p63 p69 p77 p18 p89 p11 y16 334 gnd - - p64 p70 p78 gnd* p90 gnd* gnd* - i/o -----n17p91r12y17337 i/o -----r18p92l10v16340 i/o - - - p71 p79 t18 p93 p12 w17 343 i/o - - - p72 p80 p17 p94 m11 y18 346 i/o p48 p48 p65 p73 p81 n16 p95 r13 u16 349 i/o p49 p49 p66 p74 p82 t17 p96 n12 v17 352 i/o - - p67 p75 p83 r17 p97 p13 w18 355 i/o - - p68 p76 p84 p16 p98 k10 y19 358 i/o p50 p50 p69 p77 p85 u18 p99 r14 v18 361 i/o, sgck3 ?, gck4 ?? p51 p51 p70 p78 p86 t16 p100 n13 w19 364 gnd p52 p52 p71 p79 p87 gnd* p101 gnd* gnd* - done p53 p53 p72 p80 p88 u17 p103 p14 y20 - vcc p54 p54 p73 p81 p89 vcc* p106 vcc* vcc* - pr ogram p55 p55 p74 p82 p90 v18 p108 m12 v19 - i/o (d7) p56 p56 p75 p83 p91 t15 p109 p15 u19 367 i/o, pgck3 ?, gck5 ?? p57 p57 p76 p84 p92 u16 p110 n14 u18 370 i/o - - p77 p85 p93 t14 p111 l11 t17 373 i/o - - p78 p86 p94 u15 p112 m13 v20 376 xc4010e/xl pad name pc 84 pq 100?? tq 144?? pq 160 tq 176?? pg 191? pq/h q 208 bg 225? bg 256?? bndry scan
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-125 xc4000e and xc4000x series field programmable gate arrays * pads labelled gnd* or vcc* are internally bonded to ground or vcc planes within the package. they have no direct connection to any specific package pin. ? = e only ?? = xl only additional xc4010e/xl package pins i/o (d6) p58 p58 p79 p87 p95 v17 p113 j10 t19 379 i/o - p59 p80 p88 p96 v16 p114 l12 t20 382 i/o - - - p89 p97 t13 p115 m15 r18 385 i/o - - - p90 p98 u14 p116 l13 r19 388 i/o -----v15 p117 l14 r20 391 i/o -----v14 p118 k11 p18 394 gnd - - p81 p91 p99 gnd* p119 gnd* gnd* - i/o - - p82 p92 p100 u13 p120 k13 n19 397 i/o - - p83 p93 p101 v13 p121 k14 n20 400 vcc - - - - - vcc* - vcc* vcc* - i/o (d5) p59 p60 p84 p94 p102 u12 p122 k15 m17 403 i/o ( cs0) p60 p61 p85 p95 p103 v12 p123 j12 m18 406 i/o - - - - p104 t11 p124 j13 m20 409 i/o - - - - p105 u11 p125 j14 l19 412 i/o - p62 p86 p96 p106 v11 p126 j15 l18 415 i/o - p63 p87 p97 p107 v10 p127 j11 l20 418 i/o (d4) p61 p64 p88 p98 p108 u10 p128 h13 k20 421 i/o p62 p65 p89 p99 p109 t10 p129 h14 k19 424 vcc p63 p66 p90 p100 p110 vcc* p130 vcc* vcc* - gnd p64 p67 p91 p101 p111 gnd* p131 gnd* gnd* - i/o (d3) p65 p68 p92 p102 p112 t9 p132 h12 k18 427 i/o ( rs) p66 p69 p93 p103 p113 u9 p133 h11 k17 430 i/o - p70 p94 p104 p114 v9 p134 g14 j20 433 i/o - - p95 p105 p115 v8 p135 g15 j19 436 i/o - - - - p116 u8 p136 g13 j18 439 i/o - - - - p117 t8 p137 g12 j17 442 i/o (d2) p67 p71 p96 p106 p118 v7 p138 g11 h19 445 i/o p68 p72 p97 p107 p119 u7 p139 f15 h18 448 vcc - - - - - vcc* - vcc* vcc* - i/o - - p98 p108 p120 v6 p140 f14 g19 451 i/o - - p99 p109 p121 u6 p141 f13 f20 454 gnd - - p100 p110 p122 gnd* p142 gnd* gnd* - i/o -----v5 p143 e13 d20 457 i/o -----v4 p144 d15 e18 460 i/o - - - p111 p123 u5 p145 f11 d19 463 i/o - - - p112 p124 t6 p146 d14 c20 466 i/o (d1) p69 p73 p101 p113 p125 v3 p147 e12 e17 469 i/o ( rclk, rdy/ b usy) p70 p74 p102 p114 p126 v2 p148 c15 d18 472 i/o - - p103 p115 p127 u4 p149 d13 c19 475 i/o - - p104 p116 p128 t5 p150 c14 b20 478 i/o (d0, din) p71 p75 p105 p117 p129 u3 p151 f10 c18 481 i/o, sgck4 ?, gck6 ?? (dout) p72 p76 p106 p118 p130 t4 p152 b15 b19 484 cclk p73 p77 p107 p119 p131 v1 p153 c13 a20 - vcc p74 p78 p108 p120 p132 vcc* p154 vcc* vcc* - o, tdo p75 p79 p109 p121 p133 u2 p159 a15 a19 0 gnd p76 p80 p110 p122 p134 gnd* p160 gnd* gnd* - i/o (a0, ws) p77 p81 p111 p123 p135 t3 p161 a14 b18 2 i/o, pgck4 ?, gck7 ?? (a1) p78 p82 p112 p124 p136 u1 p162 b13 b17 5 i/o - - p113 p125 p137 p3 p163 e11 c17 8 i/o - - p114 p126 p138 r2 p164 c12 d16 11 i/o (cs1, a2) p79 p83 p115 p127 p139 t2 p165 a13 a18 14 i/o (a3) p80 p84 p116 p128 p140 n3 p166 b12 a17 17 i/o - - p117 p129 p141 p2 p167 a12 a16 20 i/o - - - p130 p142 t1 p168 c11 c15 23 i/o -----r1 p169 b11 b15 26 i/o -----n2 p170 e10 a15 29 gnd - - p118 p131 p143 gnd* p171 gnd* gnd* - i/o - - p119 p132 p144 p1 p172 a11 b14 32 i/o - - p120 p133 p145 n1 p173 d10 a14 35 vcc - - - - - vcc* - vcc* vcc* - i/o (a4) p81 p85 p121 p134 p146 m2 p174 a10 c12 38 i/o (a5) p82 p86 p122 p135 p147 m1 p175 d9 b12 41 i/o - - - - p148 l3 p176 c9 a12 44 i/o - - - p136 p149 l2 p177 b9 b11 47 i/o (a21)?? - p87 p123 p137 p150 l1 p178 a9 c11 50 i/o (a20)?? - p88 p124 p138 p151 k1 p179 e9 a11 53 i/o (a6) p83 p89 p125 p139 p152 k2 p180 c8 a10 56 i/o (a7) p84 p90 p126 p140 p153 k3 p181 b8 b10 59 gnd p1 p91 p127 p141 p154 gnd* p182 gnd* gnd* - 6/19/97 xc4010e/xl pad name pc 84 pq 100?? tq 144?? pq 160 tq 176?? pg 191? pq/h q 208 bg 225? bg 256?? bndry scan pq/hq208 not connected pins p1 p3 p51 p52 p53 p54 p102 p104 p105 p107 p155 p156 p157 p158 p206 p207 p208 - - - - 5/27/97 pg191 vcc pins d3 d10 d16 j4 j15 r4 r10 r15-- --- - gnd pins c7 c12 d4 d9 d15 g3 g16 k4 k15 m3 m16 r3 r9 r16 t7 t12 - - - - - 5/27/97
r xc4000e and xc4000x series field programmable gate arrays 6-126 ds006 (v. 1.7) october 4, 1999 - product speci?cation xc4013e/xl device pinout tables the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc4000 series data sheet for availability information. bg225 vcc pins b2 b14 d8 h1 h15 r1 r8 r15 - - - - - - gnd pins a1 a8 d12 f8 g7 g8 g9 h2 h6 h7 h8 h9 h10 j7 j8 j9 k8 m8 - - - not connected pins a3 b10 c4 c6 c10 d11 e2 e3 e14 e15 f1 f2 f7 f9 f12 g10 j5 k1 k4 k12 l2 l6 l15 m10 m14 n7 n11 n15 p5 p7 p10 r10 - - - 6/16/97 bg256 vcc pins c14 d6 d7 d11 d14 d15 e20 f1 f4 f17 g4 g17 k4 l17 p4 p17 p19 r2 r4 r17 u6 u7 u10 u14 u15 v7 w20 - gnd pins a1 b7 d4 d8 d13 d17 g20 h4 h17 n3 n4 n17 u4 u8 u13 u17 w14 - - - - not connected pins a6 a7 a13 b13 b16 c4 c7 c8 c13 c16 d5 d12 e19 f2 f3 f18 f19 g18 h1 h2 h20 j3 j4 m4 m19 n1 n2 n18 p20 r3 t1 t18 u20 v9 v13 v15 w6 w9 w10 w13 w16 y6 y9 y13 y14 - - - - 5/27/97 xc4013e /xl pad name ht 144?? pq 160 ht 176?? pq/hq 208 pg 223? bg 225? pq/h q 240 bg 256?? bndry scan vcc p128 p142 p155 p183 vcc* vcc* p212 vcc* - i/o (a8) p129 p143 p156 p184 j3 e8 p213 c10 74 i/o (a9) p130 p144 p157 p185 j2 b7 p214 d10 77 i/o (a19) ?? p131 p145 p158 p186 j1 a7 p215 a9 80 i/o (a18) ?? p132 p146 p159 p187 h1 c7 p216 b9 83 i/o - - p160 p188 h2 d7 p217 c9 86 i/o - - p161 p189 h3 e7 p218 d9 89 i/o (a10) p133 p147 p162 p190 g1 a6 p220 a8 92 i/o (a11) p134 p148 p163 p191 g2 b6 p221 b8 95 vcc - - - - vcc* vcc* p222 vcc* - i/o - - - - h4 c6 p223 a6 98 i/o - - - - g4 f7 p224 c7 101 i/o p135 p149 p164 p192 f1 a5 p225 b6 104 i/o p136 p150 p165 p193 e1 b5 p226 a5 107 gnd p137 p151 p166 p194 gnd* gnd* p227 gnd* - i/o - - - p195 f2 d6 p228 c6 110 i/o - - p167 p196 d1 c5 p229 b5 113 i/o - p152 p168 p197 c1 a4 p230 a4 116 i/o - p153 p169 p198 e2 e6 p231 c5 119 i/o (a12) p138 p154 p170 p199 f3 b4 p232 b4 122 i/o (a13) p139 p155 p171 p200 d2 d5 p233 a3 125 i/o - - - - f4 a3 p234 d5 128 i/o - - - - e4 c4 p235 c4 131 i/o p140 p156 p172 p201 b1 b3 p236 b3 134 i/o p141 p157 p173 p202 e3 f6 p237 b2 137 i/o (a14) p142 p158 p174 p203 c2 a2 p238 a2 140 i/o, sgck1 ?, gck8 ?? (a15) p143 p159 p175 p204 b2 c3 p239 c3 143 vcc p144 p160 p176 p205 vcc* vcc* p240 vcc* - gnd p1 p1 p1 p2 gnd* gnd* p1 gnd* - i/o, pgck1 ?, gck1 ?? (a16) p2 p2 p2 p4 c3 d4 p2 b1 146 i/o (a17) p3 p3 p3 p5 c4 b1 p3 c2 149 i/o p4 p4 p4 p6 b3 c2 p4 d2 152 i/o p5 p5 p5 p7 c5 e5 p5 d3 155 i/o, tdi p6 p6 p6 p8 a2 d3 p6 e4 158 i/o, tck p7 p7 p7 p9 b4 c1 p7 c1 161 i/o - p8 p8 p10 c6 d2 p8 d1 164 i/o - p9 p9 p11 a3 g6 p9 e3 167 i/o - - - p12 b5 e4 p10 e2 170 i/o - - - p13 b6 d1 p11 e1 173 i/o - - - - d5 e3 p12 f3 176 i/o - - - - d6 e2 p13 f2 179 gnd p8 p10 p10 p14 gnd* gnd* p14 gnd* - i/o p9 p11 p11 p15 a4 f5 p15 g3 182 i/o p10 p12 p12 p16 a5 e1 p16 g2 185 i/o, tms p11 p13 p13 p17 b7 f4 p17 g1 188 i/o p12 p14 p14 p18 a6 f3 p18 h3 191 vcc - - - - vcc* vcc* p19 vcc* - i/o - - - - d7 f2 p20 h2 194 i/o - - - - d8 f1 p21 h1 197 i/o - - p15 p19 c8 g4 p23 j2 200 i/o - - p16 p20 a7 g3 p24 j1 203 i/o p13 p15 p17 p21 b8 g2 p25 k2 206 i/o p14 p16 p18 p22 a8 g1 p26 k3 209 i/o p15 p17 p19 p23 b9 g5 p27 k1 212 i/o p16 p18 p20 p24 c9 h3 p28 l1 215 gnd p17 p19 p21 p25 gnd* gnd* p29 gnd* - vcc p18 p20 p22 p26 vcc* vcc* p30 vcc* - i/o p19 p21 p23 p27 c10 h4 p31 l2 218 i/o p20 p22 p24 p28 b10 h5 p32 l3 221 i/o p21 p23 p25 p29 a9 j2 p33 l4 224 i/o p22 p24 p26 p30 a10 j1 p34 m1 227 i/o - - p27 p31 a11 j3 p35 m2 230 i/o - - p28 p32 c11 j4 p36 m3 233 i/o - - - - d11 j5 p38 n1 236 i/o - - - - d12 k1 p39 n2 239 vcc - - - - vcc* vcc* p40 vcc* - i/o p23 p25 p29 p33 b11 k2 p41 p1 242 i/o p24 p26 p30 p34 a12 k3 p42 p2 245 i/o p25 p27 p31 p35 b12 j6 p43 r1 248 i/o p26 p28 p32 p36 a13 l1 p44 p3 251 gnd p27 p29 p33 p37 gnd* gnd* p45 gnd* - i/o - - - - d13 l2 p46 t1 254 i/o - - - - d14 k4 p47 r3 257 i/o - - - p38 b13 l3 p48 t2 260 i/o - - - p39 a14 m1 p49 u1 263 i/o - p30 p34 p40 a15 k5 p50 t3 266 i/o - p31 p35 p41 c13 m2 p51 u2 269 i/o p28 p32 p36 p42 b14 l4 p52 v1 272 i/o p29 p33 p37 p43 a16 n1 p53 t4 275 i/o p30 p34 p38 p44 b15 m3 p54 u3 278 i/o p31 p35 p39 p45 c14 n2 p55 v2 281 i/o p32 p36 p40 p46 a17 k6 p56 w1 284 xc4013e /xl pad name ht 144?? pq 160 ht 176?? pq/hq 208 pg 223? bg 225? pq/h q 240 bg 256?? bndry scan
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-127 xc4000e and xc4000x series field programmable gate arrays i/o, sgck2 ?, gck2 ?? p33 p37 p41 p47 b16 p1 p57 v3 287 o (m1) p34 p38 p42 p48 c15 n3 p58 w2 290 gnd p35 p39 p43 p49 gnd* gnd* p59 gnd* - i (m0) p36 p40 p44 p50 a18 p2 p60 y1 293 vcc p37 p41 p45 p55 vcc* vcc* p61 vcc* - i (m2) p38 p42 p46 p56 c16 m4 p62 w3 294 i/o, pgck2 ?, gck3 ?? p39 p43 p47 p57 b17 r2 p63 y2 295 i/o (hdc) p40 p44 p48 p58 e16 p3 p64 w4 298 i/o p41 p45 p49 p59 c17 l5 p65 v4 301 i/o p42 p46 p50 p60 d17 n4 p66 u5 304 i/o p43 p47 p51 p61 b18 r3 p67 y3 307 i/o ( ldc) p44 p48 p52 p62 e17 p4 p68 y4 310 i/o - p49 p53 p63 f16 k7 p69 v5 313 i/o - p50 p54 p64 c18 m5 p70 w5 316 i/o - - - p65 d18 r4 p71 y5 319 i/o - - - p66 f17 n5 p72 v6 322 i/o - - - - e15 p5 p73 w6 325 i/o - - - - f15 l6 p74 y6 328 gnd p45 p51 p55 p67 gnd* gnd* p75 gnd* - i/o p46 p52 p56 p68 e18 r5 p76 w7 331 i/o p47 p53 p57 p69 f18 m6 p77 y7 334 i/o p48 p54 p58 p70 g17 n6 p78 v8 337 i/o p49 p55 p59 p71 g18 p6 p79 w8 340 vcc - - - - vcc* vcc* p80 vcc* - i/o - - p60 p72 h16 r6 p81 y8 343 i/o - - p61 p73 h17 m7 p82 u9 346 i/o - - - - g15 n7 p84 y9 349 i/o - - - - h15 p7 p85 w10 352 i/o p50 p56 p62 p74 h18 r7 p86 v10 355 i/o p51 p57 p63 p75 j18 l7 p87 y10 358 i/o p52 p58 p64 p76 j17 n8 p88 y11 361 i/o ( init) p53 p59 p65 p77 j16 p8 p89 w11 364 vcc p54 p60 p66 p78 vcc* vcc* p90 vcc* - gnd p55 p61 p67 p79 gnd* gnd* p91 gnd* - i/o p56 p62 p68 p80 k16 l8 p92 v11 367 i/o p57 p63 p69 p81 k17 p9 p93 u11 370 i/o p58 p64 p70 p82 k18 r9 p94 y12 373 i/o p59 p65 p71 p83 l18 n9 p95 w12 376 i/o - - p72 p84 l17 m9 p96 v12 379 i/o - - p73 p85 l16 l9 p97 u12 382 i/o - - - - l15 r10 p99 v13 385 i/o - - - - m15 p10 p100 y14 388 vcc - - - - vcc* vcc* p101 vcc* - i/o p60 p66 p74 p86 m18 n10 p102 y15 391 i/o p61 p67 p75 p87 m17 k9 p103 v14 394 i/o p62 p68 p76 p88 n18 r11 p104 w15 397 i/o p63 p69 p77 p89 p18 p11 p105 y16 400 gnd p64 p70 p78 p90 gnd* gnd* p106 gnd* - i/o - - - - n15 m10 p107 v15 403 i/o - - - - p15 n11 p108 w16 406 i/o - - - p91 n17 r12 p109 y17 409 i/o - - - p92 r18 l10 p110 v16 412 i/o - p71 p79 p93 t18 p12 p111 w17 415 i/o - p72 p80 p94 p17 m11 p112 y18 418 i/o p65 p73 p81 p95 n16 r13 p113 u16 421 i/o p66 p74 p82 p96 t17 n12 p114 v17 424 i/o p67 p75 p83 p97 r17 p13 p115 w18 427 i/o p68 p76 p84 p98 p16 k10 p116 y19 430 i/o p69 p77 p85 p99 u18 r14 p117 v18 433 i/o, sgck3 ?, gck4 ?? p70 p78 p86 p100 t16 n13 p118 w19 436 gnd p71 p79 p87 p101 gnd* gnd* p119 gnd* - done p72 p80 p88 p103 u17 p14 p120 y20 - vcc p73 p81 p89 p106 vcc* vcc* p121 vcc* - pr o- gram p74 p82 p90 p108 v18 m12 p122 v19 - i/o (d7) p75 p83 p91 p109 t15 p15 p123 u19 439 i/o, pgck3 ?, gck5 ?? p76 p84 p92 p110 u16 n14 p124 u18 442 xc4013e /xl pad name ht 144?? pq 160 ht 176?? pq/hq 208 pg 223? bg 225? pq/h q 240 bg 256?? bndry scan i/o p77 p85 p93 p111 t14 l11 p125 t17 445 i/o p78 p86 p94 p112 u15 m13 p126 v20 448 i/o - - - - r14 n15 p127 u20 451 i/o - - - - r13 m14 p128 t18 454 i/o (d6) p79 p87 p95 p113 v17 j10 p129 t19 457 i/o p80 p88 p96 p114 v16 l12 p130 t20 460 i/o - p89 p97 p115 t13 m15 p131 r18 463 i/o - p90 p98 p116 u14 l13 p132 r19 466 i/o - - - p117 v15 l14 p133 r20 469 i/o - - - p118 v14 k11 p134 p18 472 gnd p81 p91 p99 p119 gnd* gnd* p135 gnd* - i/o - - - - r12 l15 p136 p20 475 i/o - - - - r11 k12 p137 n18 478 i/o p82 p92 p100 p120 u13 k13 p138 n19 481 i/o p83 p93 p101 p121 v13 k14 p139 n20 484 vcc - - - - vcc* vcc* p140 vcc* - i/o (d5) p84 p94 p102 p122 u12 k15 p141 m17 487 i/o ( cs0) p85 p95 p103 p123 v12 j12 p142 m18 490 i/o - - p104 p124 t11 j13 p144 m20 493 i/o - - p105 p125 u11 j14 p145 l19 496 i/o p86 p96 p106 p126 v11 j15 p146 l18 499 i/o p87 p97 p107 p127 v10 j11 p147 l20 502 i/o (d4) p88 p98 p108 p128 u10 h13 p148 k20 505 i/o p89 p99 p109 p129 t10 h14 p149 k19 508 vcc p90 p100 p110 p130 vcc* vcc* p150 vcc* - gnd p91 p101 p111 p131 gnd* gnd* p151 gnd* - i/o (d3) p92 p102 p112 p132 t9 h12 p152 k18 511 i/o ( rs) p93 p103 p113 p133 u9 h11 p153 k17 514 i/o p94 p104 p114 p134 v9 g14 p154 j20 517 i/o p95 p105 p115 p135 v8 g15 p155 j19 520 i/o - - p116 p136 u8 g13 p156 j18 523 i/o - - p117 p137 t8 g12 p157 j17 526 i/o (d2) p96 p106 p118 p138 v7 g11 p159 h19 529 i/o p97 p107 p119 p139 u7 f15 p160 h18 532 vcc - - - - vcc* vcc* p161 vcc* - i/o p98 p108 p120 p140 v6 f14 p162 g19 535 i/o p99 p109 p121 p141 u6 f13 p163 f20 538 i/o - - - - r8 g10 p164 g18 541 i/o - - - - r7 e15 p165 f19 544 gnd p100 p110 p122 p142 gnd* gnd* p166 gnd* - i/o - - - - r6 e14 p167 f18 547 i/o - - - - r5 f12 p168 e19 550 i/o - - - p143 v5 e13 p169 d20 553 i/o - - - p144 v4 d15 p170 e18 556 i/o - p111 p123 p145 u5 f11 p171 d19 559 i/o - p112 p124 p146 t6 d14 p172 c20 562 i/o (d1) p101 p113 p125 p147 v3 e12 p173 e17 565 i/o ( rclk, rdy/ b us y) p102 p114 p126 p148 v2 c15 p174 d18 568 i/o p103 p115 p127 p149 u4 d13 p175 c19 571 i/o p104 p116 p128 p150 t5 c14 p176 b20 574 i/o (d0, din) p105 p117 p129 p151 u3 f10 p177 c18 577 i/o, sgck4 ?, gck6 ?? (dout) p106 p118 p130 p152 t4 b15 p178 b19 580 cclk p107 p119 p131 p153 v1 c13 p179 a20 - vcc p108 p120 p132 p154 vcc* vcc* p180 vcc* - o, tdo p109 p121 p133 p159 u2 a15 p181 a19 0 gnd p110 p122 p134 p160 gnd* gnd* p182 gnd* - i/o (a0, ws) p111 p123 p135 p161 t3 a14 p183 b18 2 i/o, pgck4 ?, gck7 ?? (a1) p112 p124 p136 p162 u1 b13 p184 b17 5 i/o p113 p125 p137 p163 p3 e11 p185 c17 8 i/o p114 p126 p138 p164 r2 c12 p186 d16 11 i/o (cs1, a2) p115 p127 p139 p165 t2 a13 p187 a18 14 i/o (a3) p116 p128 p140 p166 n3 b12 p188 a17 17 i/o - - - - p4 f9 p189 c16 20 i/o - - - - n4 d11 p190 b16 23 xc4013e /xl pad name ht 144?? pq 160 ht 176?? pq/hq 208 pg 223? bg 225? pq/h q 240 bg 256?? bndry scan
r xc4000e and xc4000x series field programmable gate arrays 6-128 ds006 (v. 1.7) october 4, 1999 - product speci?cation * pads labelled gnd* or vcc* are internally bonded to ground or vcc planes within the package. they have no direct connection to any specific package pin. ? = e only, ?? = xl only additional xc4013e/xl package pins the bg225 package pins in this table are bonded to an internal ground plane on the xc4013e die. they must all be externally con- nected to ground. ? pins marked with this symbol are used for ground connections on some revisions of the device. these pins may not physically con- nect to anything on the current device revision. however, they should be externally connected to ground, if possible. i/o p117 p129 p141 p167 p2 a12 p191 a16 26 i/o - p130 p142 p168 t1 c11 p192 c15 29 i/o - - - p169 r1 b11 p193 b15 32 i/o - - - p170 n2 e10 p194 a15 35 gnd p118 p131 p143 p171 gnd* gnd* p196 gnd* - i/o p119 p132 p144 p172 p1 a11 p197 b14 38 i/o p120 p133 p145 p173 n1 d10 p198 a14 41 i/o - - - - m4 c10 p199 c13 44 i/o - - - - l4 b10 p200 b13 47 vcc - - - - vcc* vcc* p201 vcc* - i/o (a4) p121 p134 p146 p174 m2 a10 p202 c12 50 i/o (a5) p122 p135 p147 p175 m1 d9 p203 b12 53 i/o - - p148 p176 l3 c9 p205 a12 56 i/o - p136 p149 p177 l2 b9 p206 b11 59 i/o (a21) ?? p123 p137 p150 p178 l1 a9 p207 c11 62 i/o (a20) ?? p124 p138 p151 p179 k1 e9 p208 a11 65 i/o (a6) p125 p139 p152 p180 k2 c8 p209 a10 68 i/o (a7) p126 p140 p153 p181 k3 b8 p210 b10 71 gnd p127 p141 p154 p182 gnd* gnd* p211 gnd* - 6/9/97 pq/hq208 not connected pins p1 p3 p51 p52 p53 p54 p102 p104 p105 p107 p155 p156 p157 p158 p206 p207 p208 - 5/5/97 pg223 vcc pins d3 d10 d16 j4 j15 r4 r10 r15 - - - - gnd pins c7 c12 d4 d9 d15 g3 g16 k4 k15 m3 m16 r3 r9 r16 t7 t12 - - 5/5/97 xc4013e /xl pad name ht 144?? pq 160 ht 176?? pq/hq 208 pg 223? bg 225? pq/h q 240 bg 256?? bndry scan bg225 vcc pins b2 b14 d8 h1 h15 r1 r8 r15 - - gnd pins a1 a8 d12 f8 g7 g8 g9 h2 h6 h7 h8 h9 h10 j7 j8 j9 k8 m8 - - 5/5/97 pq/hq240 gnd pins p22? p37? p83? p98? p143? p158? p204? p219? - - - - not connected pins p195 ----- 6/9/97 bg256 vcc pins c14 d6 d7 d11 d14 d15 e20 f1 f4 f17 g4 g17 k4 l17 p4 p17 p19 r2 r4 r17 u6 u7 u10 u14 u15 v7 w20 - - - gnd pins a1 b7 d4 d8 d13 d17 g20 h4 h17 n3 n4 n17 u4 u8 u13 u17 w14 - not connected pins a7 a13 c8 d12 h20 j3 j4 m4 m19 v9 w9 w13 y13----- 6/4/97
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-129 xc4000e and xc4000x series field programmable gate arrays xc4020e/xl device pinout tables the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc4000 series data sheet for availability information. xc4020e/xl pad name ht 144?? pq 160?? ht 176?? hq208? pq208?? pg 223? hq240? pq240?? bg 256?? bndry scan vcc p128 p142 p155 p183 vcc* p212 vcc* - i/o (a8) p129 p143 p156 p184 j3 p213 c10 86 i/o (a9) p130 p144 p157 p185 j2 p214 d10 89 i/o (a19) ?? p131 p145 p158 p186 j1 p215 a9 92 i/o (a18) ?? p132 p146 p159 p187 h1 p216 b9 95 i/o - - p160 p188 h2 p217 c9 98 i/o - - p161 p189 h3 p218 d9 101 i/o (a10) p133 p147 p162 p190 g1 p220 a8 104 i/o (a11) p134 p148 p163 p191 g2 p221 b8 107 i/o - - - - - - c8 110 i/o - - - - - - a7 113 vcc - - - - vcc* p222 vcc* - i/o - - - - h4 p223 a6 116 i/o - - - - g4 p224 c7 119 i/o p135 p149 p164 p192 f1 p225 b6 122 i/o p136 p150 p165 p193 e1 p226 a5 125 gnd p137 p151 p166 p194 gnd* p227 gnd* - i/o - - - p195 f2 p228 c6 128 i/o - - p167 p196 d1 p229 b5 131 i/o - p152 p168 p197 c1 p230 a4 134 i/o - p153 p169 p198 e2 p231 c5 137 i/o (a12) p138 p154 p170 p199 f3 p232 b4 140 i/o (a13) p139 p155 p171 p200 d2 p233 a3 143 i/o - - - - f4 p234 d5 152 i/o - - - - e4 p235 c4 155 i/o p140 p156 p172 p201 b1 p236 b3 158 i/o p141 p157 p173 p202 e3 p237 b2 161 i/o (a14) p142 p158 p174 p203 c2 p238 a2 164 i/o, sgck1 ?, gck8 ?? (a15) p143 p159 p175 p204 b2 p239 c3 167 vcc p144 p160 p176 p205 vcc* p240 vcc* - gnd p1 p1 p1 p2 gnd* p1 gnd* - i/o, pgck1 ?, gck1 ?? (a16) p2 p2 p2 p4 c3 p2 b1 170 i/o (a17) p3 p3 p3 p5 c4 p3 c2 173 i/o p4 p4 p4 p6 b3 p4 d2 176 i/o p5 p5 p5 p7 c5 p5 d3 179 i/o, tdi p6 p6 p6 p8 a2 p6 e4 182 i/o, tck p7 p7 p7 p9 b4 p7 c1 185 i/o - p8 p8 p10 c6 p8 d1 194 i/o - p9 p9 p11 a3 p9 e3 197 i/o - - - p12 b5 p10 e2 200 i/o - - - p13 b6 p11 e1 203 i/o - - - - d5 p12 f3 206 i/o - - - - d6 p13 f2 209 gnd p8 p10 p10 p14 gnd* p14 gnd* - i/o p9 p11 p11 p15 a4 p15 g3 212 i/o p10 p12 p12 p16 a5 p16 g2 215 i/o, tms p11 p13 p13 p17 b7 p17 g1 218 i/o p12 p14 p14 p18 a6 p18 h3 221 vcc - - - - vcc* p19 vcc* - i/o - - - - d7 p20 h2 224 i/o - - - - d8 p21 h1 227 i/o - - - - - - j4 230 i/o - - - - - - j3 233 i/o - - p15 p19 c8 p23 j2 236 i/o - - p16 p20 a7 p24 j1 239 i/o p13 p15 p17 p21 b8 p25 k2 242 i/o p14 p16 p18 p22 a8 p26 k3 245 i/o p15 p17 p19 p23 b9 p27 k1 248 i/o p16 p18 p20 p24 c9 p28 l1 251 gnd p17 p19 p21 p25 gnd* p29 gnd* - vcc p18 p20 p22 p26 vcc* p30 vcc* - i/o p19 p21 p23 p27 c10 p31 l2 254 i/o p20 p22 p24 p28 b10 p32 l3 257 i/o p21 p23 p25 p29 a9 p33 l4 260 i/o p22 p24 p26 p30 a10 p34 m1 263 i/o - - p27 p31 a11 p35 m2 266 i/o - - p28 p32 c11 p36 m3 269 i/o ------m4272 i/o - - - - d11 p38 n1 278 i/o - - - - d12 p39 n2 281 vcc - - - - vcc* p40 vcc* - i/o p23 p25 p29 p33 b11 p41 p1 284 i/o p24 p26 p30 p34 a12 p42 p2 287 i/o p25 p27 p31 p35 b12 p43 r1 290 i/o p26 p28 p32 p36 a13 p44 p3 293 gnd p27 p29 p33 p37 gnd* p45 gnd* - i/o - - - - d13 p46 t1 296 i/o - - - - d14 p47 r3 299 i/o - - - p38 b13 p48 t2 302 i/o - - - p39 a14 p49 u1 305 i/o - p30 p34 p40 a15 p50 t3 308 i/o - p31 p35 p41 c13 p51 u2 311 i/o p28 p32 p36 p42 b14 p52 v1 320 i/o p29 p33 p37 p43 a16 p53 t4 323 i/o p30 p34 p38 p44 b15 p54 u3 326 i/o p31 p35 p39 p45 c14 p55 v2 329 i/o p32 p36 p40 p46 a17 p56 w1 332 i/o, sgck2 ?, gck2 ?? p33 p37 p41 p47 b16 p57 v3 335 o (m1) p34 p38 p42 p48 c15 p58 w2 338 gnd p35 p39 p43 p49 gnd* p59 gnd* - i (m0) p36 p40 p44 p50 a18 p60 y1 341 vcc p37 p41 p45 p55 vcc* p61 vcc* - i (m2) p38 p42 p46 p56 c16 p62 w3 342 i/o pgck2 ?, gck3 ?? p39 p43 p47 p57 b17 p63 y2 343 i/o (hdc) p40 p44 p48 p58 e16 p64 w4 346 i/o p41 p45 p49 p59 c17 p65 v4 349 i/o p42 p46 p50 p60 d17 p66 u5 352 i/o p43 p47 p51 p61 b18 p67 y3 355 i/o ( ldc) p44 p48 p52 p62 e17 p68 y4 358 i/o - p49 p53 p63 f16 p69 v5 367 i/o - p50 p54 p64 c18 p70 w5 370 i/o - - - p65 d18 p71 y5 373 i/o - - - p66 f17 p72 v6 376 i/o - - - - e15 p73 w6 379 i/o - - - - f15 p74 y6 382 gnd p45 p51 p55 p67 gnd* p75 gnd* - i/o p46 p52 p56 p68 e18 p76 w7 385 i/o p47 p53 p57 p69 f18 p77 y7 388 i/o p48 p54 p58 p70 g17 p78 v8 391 i/o p49 p55 p59 p71 g18 p79 w8 394 vcc - - - - vcc* p80 vcc* - i/o - - p60 p72 h16 p81 y8 397 i/o - - p61 p73 h17 p82 u9 400 i/o ------v9403 i/o ------w9406 i/o - - - - g15 p84 y9 409 i/o - - - - h15 p85 w10 412 i/o p50 p56 p62 p74 h18 p86 v10 415 i/o p51 p57 p63 p75 j18 p87 y10 418 i/o p52 p58 p64 p76 j17 p88 y11 421 i/o ( init) p53 p59 p65 p77 j16 p89 w11 424 vcc p54 p60 p66 p78 vcc* p90 vcc* - gnd p55 p61 p67 p79 gnd* p91 gnd* - i/o p56 p62 p68 p80 k16 p92 v11 427 i/o p57 p63 p69 p81 k17 p93 u11 430 i/o p58 p64 p70 p82 k18 p94 y12 433 i/o p59 p65 p71 p83 l18 p95 w12 436 i/o - - p72 p84 l17 p96 v12 439 i/o - - p73 p85 l16 p97 u12 442 i/o ------y13445 i/o ------w13448 i/o - - - - l15 p99 v13 451 i/o - - - - m15 p100 y14 454 vcc - - - - vcc* p101 vcc* - i/o p60 p66 p74 p86 m18 p102 y15 457 i/o p61 p67 p75 p87 m17 p103 v14 460 i/o p62 p68 p76 p88 n18 p104 w15 463 i/o p63 p69 p77 p89 p18 p105 y16 466 gnd p64 p70 p78 p90 gnd* p106 gnd* - i/o - - - - n15 p107 v15 469 i/o - - - - p15 p108 w16 472 i/o - - - p91 n17 p109 y17 475 i/o - - - p92 r18 p110 v16 478 i/o - p71 p79 p93 t18 p111 w17 481 i/o - p72 p80 p94 p17 p112 y18 484 xc4020e/xl pad name ht 144?? pq 160?? ht 176?? hq208? pq208?? pg 223? hq240? pq240?? bg 256?? bndry scan
r xc4000e and xc4000x series field programmable gate arrays 6-130 ds006 (v. 1.7) october 4, 1999 - product speci?cation ? = e only ?? = xl only additional xc4020e/xl package pins ? pins marked with this symbol are used for ground connections on some revisions of the device. these pins may not physically con- nect to anything on the current device revision. however, they should be externally connected to ground, if possible. i/o p65 p73 p81 p95 n16 p113 u16 493 i/o p66 p74 p82 p96 t17 p114 v17 496 i/o p67 p75 p83 p97 r17 p115 w18 499 i/o p68 p76 p84 p98 p16 p116 y19 502 i/o p69 p77 p85 p99 u18 p117 v18 505 i/o, sgck3 ?, gck4 ?? p70 p78 p86 p100 t16 p118 w19 508 gnd p71 p79 p87 p101 gnd* p119 gnd* - done p72 p80 p88 p103 u17 p120 y20 - vcc p73 p81 p89 p106 vcc* p121 vcc* - program p74 p82 p90 p108 v18 p122 v19 - i/o (d7) p75 p83 p91 p109 t15 p123 u19 511 i/o, pgck3 ?, gck5 ?? p76 p84 p92 p110 u16 p124 u18 514 i/o p77 p85 p93 p111 t14 p125 t17 517 i/o p78 p86 p94 p112 u15 p126 v20 520 i/o - - - - r14 p127 u20 523 i/o - - - - r13 p128 t18 526 i/o (d6) p79 p87 p95 p113 v17 p129 t19 535 i/o p80 p88 p96 p114 v16 p130 t20 538 i/o - p89 p97 p115 t13 p131 r18 541 i/o - p90 p98 p116 u14 p132 r19 544 i/o - - - p117 v15 p133 r20 547 i/o - - - p118 v14 p134 p18 550 gnd p81 p91 p99 p119 gnd* p135 gnd* - i/o - - - - r12 p136 p20 553 i/o - - - - r11 p137 n18 556 i/o p82 p92 p100 p120 u13 p138 n19 559 i/o p83 p93 p101 p121 v13 p139 n20 562 vcc - - - - vcc* p140 vcc* - i/o (d5) p84 p94 p102 p122 u12 p141 m17 565 i/o (cs0) p85 p95 p103 p123 v12 p142 m18 568 i/o ------m19574 i/o - - p104 p124 t11 p144 m20 577 i/o - - p105 p125 u11 p145 l19 580 i/o p86 p96 p106 p126 v11 p146 l18 583 i/o p87 p97 p107 p127 v10 p147 l20 586 i/o (d4) p88 p98 p108 p128 u10 p148 k20 589 i/o p89 p99 p109 p129 t10 p149 k19 592 vcc p90 p100 p110 p130 vcc* p150 vcc* - gnd p91 p101 p111 p131 gnd* p151 gnd* - i/o (d3) p92 p102 p112 p132 t9 p152 k18 595 i/o (rs) p93 p103 p113 p133 u9 p153 k17 598 i/o p94 p104 p114 p134 v9 p154 j20 601 i/o p95 p105 p115 p135 v8 p155 j19 604 i/o - - p116 p136 u8 p156 j18 607 i/o - - p117 p137 t8 p157 j17 610 i/o ------h20613 i/o (d2) p96 p106 p118 p138 v7 p159 h19 619 i/o p97 p107 p119 p139 u7 p160 h18 622 vcc - - - vcc* p161 vcc* - i/o p98 p108 p120 p140 v6 p162 g19 625 i/o p99 p109 p121 p141 u6 p163 f20 628 i/o - - - - r8 p164 g18 631 i/o - - - - r7 p165 f19 634 gnd p100 p110 p122 p142 gnd* p166 gnd* - i/o - - - - r6 p167 f18 637 i/o - - - - r5 p168 e19 640 i/o - - - p143 v5 p169 d20 643 i/o - - - p144 v4 p170 e18 646 i/o - p111 p123 p145 u5 p171 d19 649 i/o - p112 p124 p146 t6 p172 c20 652 i/o (d1) p101 p113 p125 p147 v3 p173 e17 655 i/o (rclk, rdy/busy) p102 p114 p126 p148 v2 p174 d18 658 i/o p103 p115 p127 p149 u4 p175 c19 667 i/o p104 p116 p128 p150 t5 p176 b20 670 i/o (d0, din) p105 p117 p129 p151 u3 p177 c18 673 i/o, sgck4 ?, gck6 ?? (dout) p106 p118 p130 p152 t4 p178 b19 676 cclk p107 p119 p131 p153 v1 p179 a20 - vcc p108 p120 p132 p154 vcc* p180 vcc* - o, tdo p109 p121 p133 p159 u2 p181 a19 0 gnd p110 p122 p134 p160 gnd* p182 gnd* - i/o (a0, ws) p111 p123 p135 p161 t3 p183 b18 2 i/o, pgck4 ?, gck7 ?? (a1) p112 p124 p136 p162 u1 p184 b17 5 i/o p113 p125 p137 p163 p3 p185 c17 8 i/o p114 p126 p138 p164 r2 p186 d16 11 i/o (cs1, a2) p115 p127 p139 p165 t2 p187 a18 14 i/o (a3) p116 p128 p140 p166 n3 p188 a17 17 xc4020e/xl pad name ht 144?? pq 160?? ht 176?? hq208? pq208?? pg 223? hq240? pq240?? bg 256?? bndry scan i/o - - - - p4 p189 c16 26 i/o - - - - n4 p190 b16 29 i/o p117 p129 p141 p167 p2 p191 a16 32 i/o - p130 p142 p168 t1 p192 c15 35 i/o - - - p169 r1 p193 b15 38 i/o - - - p170 n2 p194 a15 41 gnd p118 p131 p143 p171 gnd* p196 gnd* - i/o p119 p132 p144 p172 p1 p197 b14 44 i/o p120 p133 p145 p173 n1 p198 a14 47 i/o - - - - m4 p199 c13 50 i/o - - - - l4 p200 b13 53 vcc - - - - vcc* p201 vcc* - i/o ------a1356 i/o ------d1259 i/o (a4) p121 p134 p146 p174 m2 p202 c12 62 i/o (a5) p122 p135 p147 p175 m1 p203 b12 65 i/o - - p148 p176 l3 p205 a12 68 i/o - p136 p149 p177 l2 p206 b11 71 i/o (a21) ?? p123 p137 p150 p178 l1 p207 c11 74 i/o (a20) ?? p124 p138 p151 p179 k1 p208 a11 77 i/o (a6) p125 p139 p152 p180 k2 p209 a10 80 i/o (a7) p126 p140 p153 p181 k3 p210 b10 83 gnd p127 p141 p154 p182 gnd* p211 gnd* - 6/24/97 pq/hq208 not connected pins p1 p3 p51 p52 p53 p54 p102 p104 p105 p107 p155 p156 p157 p158 p206 p207 p208 - 5/5/97 pg223 vcc pins d3 d10 d16 j4 j15 r4 r10 r15 - - - - gnd pins c7 c12 d4 d9 d15 g3 g16 k4 k15 m3 m16 r3 r9 r16 t7 t12 - - 5/5/97 pq/hq240 gnd pins p22? p37? p83? p98? p143? p158? p204? p219? - - - - not connected pins p195 ----- 6/9/97 bg256 vcc pins c14 d6 d7 d11 d14 d15 e20 f1 f4 f17 g4 g17 k4 l17 p4 p17 p19 r2 r4 r17 u6 u7 u10 u14 u15 v7 w20 - - - gnd pins a1 b7 d4 d8 d13 d17 g20 h4 h17 n3 n4 n17 u4 u8 u13 u17 w14 - 6/17/97 xc4020e/xl pad name ht 144?? pq 160?? ht 176?? hq208? pq208?? pg 223? hq240? pq240?? bg 256?? bndry scan
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-131 xc4000e and xc4000x series field programmable gate arrays xc4025e, xc4028ex/xl device pinout tables the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc4000 series data sheet for availability information. xc4025e, xc4028** ex/xl pad name hq 160?? hq 208? pg 223? hq 240 bg 256?? pg 299 hq 304 bg 352? bndry scan vcc p142 p183 vcc* p212 vcc* vcc* p38 vcc* - i/o (a8) p143 p184 j3 p213 c10 k2 p37 d14 98 i/o (a9) p144 p185 j2 p214 d10 k3 p36 c14 101 i/o (a19) ? p145 p186 j1 p215 a9 k5 p35 a15 104 i/o (a18) ? p146 p187 h1 p216 b9 k4 p34 b15 107 i/o - p188 h2 p217 c9 j1 p33 c15 110 i/o - p189 h3 p218 d9 j2 p32 d15 113 i/o (a10) p147 p190 g1 p220 a8 h1 p31 a16 116 i/o (a11) p148 p191 g2 p221 b8 j3 p30 b16 119 gnd - - - - gnd* gnd* - gnd* - i/o - - - - - j4 p29 c16 122 i/o - - - - - j5 p28 b17 125 i/o - - - - c8 h2 p27 c17 128 i/o - - - - a7 g1 p26 b18 131 vcc - - vcc* p222 vcc* vcc* p25 vcc* - i/o - - h4 p223 a6 h3 p23 c18 134 i/o - - g4 p224 c7 g2 p22 d17 137 i/o p149 p192 f1 p225 b6 h4 p21 a20 140 i/o p150 p193 e1 p226 a5 f2 p20 b19 143 gnd p151 p194 gnd* p227 gnd* gnd* p19 gnd* - i/o - - - - - h5 p18 c19 146 i/o - - - - - g3 p17 d18 149 i/o - p195 f2 p228 c6 d1 p16 a21 152 i/o - p196 d1 p229 b5 g4 p15 b20 155 i/o p152 p197 c1 p230 a4 e2 p14 c20 158 i/o p153 p198 e2 p231 c5 f3 p13 b21 161 i/o (a12) p154 p199 f3 p232 b4 g5 p12 b22 164 i/o (a13) p155 p200 d2 p233 a3 c1 p10 c21 167 gnd - - - - gnd* gnd* - gnd* - vcc - - - - vcc* vcc* - vcc* - i/o - - - - - f4 p9 d20 170 i/o - - - - - e3 p8 a23 173 i/o - - f4 p234 d5 d2 p7 d21 176 i/o - - e4 p235 c4 c2 p6 c22 179 i/o p156 p201 b1 p236 b3 f5 p5 b24 182 i/o p157 p202 e3 p237 b2 e4 p4 c23 185 i/o (a14) p158 p203 c2 p238 a2 d3 p3 d22 188 i/o, sgck1 ?, gck8 ? (a15) p159 p204 b2 p239 c3 c3 p2 c24 191 vcc p160 p205 vcc* p240 vcc* vcc* p1 vcc* - gnd p1 p2 gnd* p1 gnd* gnd* p304 gnd* - i/o, pgck1 ?, gck1 ? (a16) p2 p4 c3 p2 b1 d4 p303 d23 194 i/o (a17) p3 p5 c4 p3 c2 b2 p302 c25 197 i/o p4 p6 b3 p4 d2 b3 p301 d24 200 i/o p5 p7 c5 p5 d3 e6 p300 e23 203 i/o, tdi p6 p8 a2 p6 e4 d5 p299 c26 206 i/o, tck p7 p9 b4 p7 c1 c4 p298 e24 209 i/o - - - - - a3 p297 f24 212 i/o - - - - - d6 p296 e25 215 vcc - - - - vcc* vcc* - vcc* - gnd - - - - gnd* gnd* - gnd* - i/o p8 p10 c6 p8 d1 e7 p295 d26 218 i/o p9 p11 a3 p9 e3 b4 p294 g24 221 i/o - p12 b5 p10 e2 c5 p293 f25 224 i/o - p13 b6 p11 e1 a4 p292 f26 227 i/o - - d5 p12 f3 d7 p291 h23 230 i/o - - d6 p13 f2 c6 p290 h24 233 i/o - - - - - e8 p289 g25 236 i/o - - - - - b5 p288 g26 239 gnd p10 p14 gnd* p14 gnd* gnd* p287 gnd* - i/o p11 p15 a4 p15 g3 b6 p286 j23 242 i/o p12 p16 a5 p16 g2 d8 p285 j24 245 i/o, tms p13 p17 b7 p17 g1 c7 p284 h25 248 i/o p14 p18 a6 p18 h3 b7 p283 k23 251 vcc - - vcc* p19 vcc* vcc* p282 vcc* - i/o - - d7 p20 h2 c8 p280 k24 254 i/o - - d8 p21 h1 e9 p279 j25 257 i/o - - - - - a7 p278 l24 260 i/o - - - - - d9 p277 k25 263 gnd - - - p22 gnd* gnd* - gnd* - i/o - - - - j4 b8 p276 l25 266 i/o - - - - j3 a8 p275 l26 269 i/o - p19 c8 p23 j2 c9 p274 m23 272 i/o - p20 a7 p24 j1 b9 p273 m24 275 i/o p15 p21 b8 p25 k2 e10 p272 m25 278 i/o p16 p22 a8 p26 k3 a9 p271 m26 281 i/o p17 p23 b9 p27 k1 d10 p270 n24 284 i/o p18 p24 c9 p28 l1 c10 p269 n25 287 gnd p19 p25 gnd* p29 gnd* gnd* p268 gnd* - vcc p20 p26 vcc* p30 vcc* vcc* p267 vcc* - i/o p21 p27 c10 p31 l2 b10 p266 n26 290 i/o p22 p28 b10 p32 l3 b11 p265 p25 293 i/o p23 p29 a9 p33 l4 c11 p264 p23 296 i/o p24 p30 a10 p34 m1 e11 p263 p24 299 i/o - p31 a11 p35 m2 d11 p262 r26 302 i/o - p32 c11 p36 m3 a12 p261 r25 305 i/o - - - - m4 b12 p260 r24 308 i/o - - - - - a13 p259 r23 311 gnd - - - p37 gnd* gnd* - gnd* - i/o - - - - - c12 p258 t26 314 i/o - - - - - d12 p257 t25 317 i/o - - d11 p38 n1 e12 p256 t23 320 i/o - - d12 p39 n2 b13 p255 v26 323 vcc - - vcc* p40 vcc* vcc* p253 vcc* - i/o p25 p33 b11 p41 p1 a14 p252 u24 326 i/o p26 p34 a12 p42 p2 c13 p251 v25 329 i/o p27 p35 b12 p43 r1 b14 p250 v24 332 i/o p28 p36 a13 p44 p3 d13 p249 u23 335 gnd p29 p37 gnd* p45 gnd* gnd* p248 gnd* - i/o - - - - - b15 p247 y26 338 i/o - - - - - e13 p246 w25 341 i/o - - d13 p46 t1 c14 p245 w24 344 i/o - - d14 p47 r3 a17 p244 v23 347 i/o - p38 b13 p48 t2 d14 p243 aa26 350 i/o - p39 a14 p49 u1 b16 p242 y25 353 i/o p30 p40 a15 p50 t3 c15 p241 y24 356 i/o p31 p41 c13 p51 u2 e14 p240 aa25 359 gnd - - - - gnd* gnd* - gnd* - vcc - - - - vcc* vcc* - vcc* - i/o - - - - - a18 p239 ab25 362 i/o - - - - - d15 p238 aa24 365 i/o p32 p42 b14 p52 v1 c16 p237 y23 368 i/o p33 p43 a16 p53 t4 b17 p236 ac26 371 i/o p34 p44 b15 p54 u3 b18 p235 aa23 374 i/o p35 p45 c14 p55 v2 e15 p234 ab24 377 i/o p36 p46 a17 p56 w1 d16 p233 ad25 380 i/o, sgck2 ?, gck2 ? p37 p47 b16 p57 v3 c17 p232 ac24 383 o (m1) p38 p48 c15 p58 w2 a20 p231 ab23 386 gnd p39 p49 gnd* p59 gnd* gnd* p230 gnd* - xc4025e, xc4028** ex/xl pad name hq 160?? hq 208? pg 223? hq 240 bg 256?? pg 299 hq 304 bg 352? bndry scan
r xc4000e and xc4000x series field programmable gate arrays 6-132 ds006 (v. 1.7) october 4, 1999 - product speci?cation i (m0) p40 p50 a18 p60 y1 c18 p229 ad24 389 vcc p41 p55 vcc* p61 vcc* vcc* p228 vcc* - i (m2) p42 p56 c16 p62 w3 d17 p227 ac23 390 i/o, pgck2 ?, gck3 ? p43 p57 b17 p63 y2 b19 p226 ae24 391 i/o (hdc) p44 p58 e16 p64 w4 c19 p225 ad23 394 i/o p45 p59 c17 p65 v4 f16 p224 ac22 397 i/o p46 p60 d17 p66 u5 e17 p223 af24 400 i/o p47 p61 b18 p67 y3 d18 p222 ad22 403 i/o ( ldc) p48 p62 e17 p68 y4 c20 p221 ae23 406 i/o - - - - - f17 p220 ae22 409 i/o - - - - - g16 p219 af23 412 vcc - - - - vcc* vcc* - vcc* - gnd - - - - gnd* gnd* - gnd* - i/o p49 p63 f16 p69 v5 d19 p218 ad20 415 i/o p50 p64 c18 p70 w5 e18 p217 ae21 418 i/o - p65 d18 p71 y5 d20 p216 af21 421 i/o - p66 f17 p72 v6 g17 p215 ac19 424 i/o - - e15 p73 w6 f18 p214 ad19 427 i/o - - f15 p74 y6 h16 p213 ae20 430 i/o - - - - - e19 p212 af20 433 i/o - - - - - f19 p211 ac18 436 gnd p51 p67 gnd* p75 gnd* gnd* p210 gnd* - i/o p52 p68 e18 p76 w7 h17 p209 ad18 439 i/o p53 p69 f18 p77 y7 g18 p208 ae19 442 i/o p54 p70 g17 p78 v8 g19 p207 ac17 445 i/o p55 p71 g18 p79 w8 h18 p206 ad17 448 vcc - - vcc* p80 vcc* vcc* p204 vcc* - i/o - p72 h16 p81 y8 j16 p203 ae18 451 i/o - p73 h17 p82 u9 g20 p202 af18 454 i/o - - - - - j17 p201 ae17 457 i/o - - - - - h19 p200 ae16 460 gnd - - - p83 gnd* gnd* - gnd* - i/o - - - - v9 h20 p199 af16 463 i/o - - - - w9 j18 p198 ac15 466 i/o - - g15 p84 y9 j19 p197 ad15 469 i/o - - h15 p85 w10 k16 p196 ae15 472 i/o p56 p74 h18 p86 v10 j20 p195 af15 475 i/o p57 p75 j18 p87 y10 k17 p194 ad14 478 i/o p58 p76 j17 p88 y11 k18 p193 ae14 481 i/o ( init) p59 p77 j16 p89 w11 k19 p192 af14 484 vcc p60 p78 vcc* p90 vcc* vcc* p191 vcc* - gnd p61 p79 gnd* p91 gnd* gnd* p190 gnd* - i/o p62 p80 k16 p92 v11 l19 p189 ae13 487 i/o p63 p81 k17 p93 u11 l18 p188 ac13 490 i/o p64 p82 k18 p94 y12 l16 p187 ad13 493 i/o p65 p83 l18 p95 w12 l17 p186 af12 496 i/o - p84 l17 p96 v12 m20 p185 ae12 499 i/o - p85 l16 p97 u12 m19 p184 ad12 502 i/o - - - - y13 n20 p183 ac12 505 i/o - - - - w13 m18 p182 af11 508 gnd - - - p98 gnd* gnd* - gnd* - i/o - - - - - m17 p181 ae11 511 i/o - - - - - m16 p180 ad11 514 i/o - - l15 p99 v13 n19 p179 af9 517 i/o - - m15 p100 y14 p20 p178 ad10 520 vcc - - vcc* p101 vcc* vcc* p177 vcc* - i/o p66 p86 m18 p102 y15 n18 p175 ae9 523 i/o p67 p87 m17 p103 v14 p19 p174 ad9 526 i/o p68 p88 n18 p104 w15 n17 p173 ac10 529 i/o p69 p89 p18 p105 y16 r19 p172 af7 532 gnd p70 p90 gnd* p106 gnd* gnd* p171 gnd* - i/o - - - - - n16 p170 ae8 535 i/o - - - - - p18 p169 ad8 538 i/o - - n15 p107 v15 u20 p168 ac9 541 i/o - - p15 p108 w16 p17 p167 af6 544 i/o - p91 n17 p109 y17 t19 p166 ae7 547 xc4025e, xc4028** ex/xl pad name hq 160?? hq 208? pg 223? hq 240 bg 256?? pg 299 hq 304 bg 352? bndry scan i/o - p92 r18 p110 v16 r18 p165 ad7 550 i/o p71 p93 t18 p111 w17 p16 p164 ae6 553 i/o p72 p94 p17 p112 y18 v20 p163 ae5 556 gnd - - - - gnd* gnd* - gnd* - vcc - - - - vcc* vcc* - vcc* - i/o - - - - - r17 p162 ad6 559 i/o - - - - - t18 p161 ac7 562 i/o p73 p95 n16 p113 u16 u19 p160 af4 565 i/o p74 p96 t17 p114 v17 v19 p159 af3 568 i/o p75 p97 r17 p115 w18 r16 p158 ad5 571 i/o p76 p98 p16 p116 y19 t17 p157 ae3 574 i/o p77 p99 u18 p117 v18 u18 p156 ad4 577 i/o, sgck3 ?, gck4 ? p78 p100 t16 p118 w19 x20 p155 ac5 580 gnd p79 p101 gnd* p119 gnd* gnd* p154 gnd* - done p80 p103 u17 p120 y20 v18 p153 ad3 - vcc p81 p106 vcc* p121 vcc* vcc* p152 vcc* - pr o- gram p82 p108 v18 p122 v19 u17 p151 ac4 - i/o (d7) p83 p109 t15 p123 u19 w19 p150 ad2 583 i/o, pgck3 ?, gck5 ? p84 p110 u16 p124 u18 w18 p149 ac3 586 i/o p85 p111 t14 p125 t17 t15 p148 ab4 589 i/o p86 p112 u15 p126 v20 u16 p147 ad1 592 i/o - - r14 p127 u20 v17 p146 aa4 595 i/o - - r13 p128 t18 x18 p145 aa3 598 i/o - - - - - u15 p144 ab2 601 i/o - - - - - t14 p143 ac1 604 vcc - - - - vcc* vcc* - vcc* - gnd - - - - gnd* gnd* - gnd* - i/o (d6) p87 p113 v17 p129 t19 w17 p142 y3 607 i/o p88 p114 v16 p130 t20 v16 p141 aa2 610 i/o p89 p115 t13 p131 r18 x17 p140 aa1 613 i/o p90 p116 u14 p132 r19 u14 p139 w4 616 i/o - p117 v15 p133 r20 v15 p138 w3 619 i/o - p118 v14 p134 p18 t13 p137 y2 622 i/o - - - - - w16 p136 y1 625 i/o - - - - - w15 p135 v4 628 gnd p91 p119 gnd* p135 gnd* gnd* p134 gnd* - i/o - - r12 p136 p20 u13 p133 v3 631 i/o - - r11 p137 n18 v14 p132 w2 634 i/o p92 p120 u13 p138 n19 w14 p131 u4 637 i/o p93 p121 v13 p139 n20 v13 p130 u3 640 vcc - - vcc* p140 vcc* vcc* p129 vcc* - i/o (d5) p94 p122 u12 p141 m17 t12 p127 v2 643 i/o ( cs0) p95 p123 v12 p142 m18 x14 p126 v1 646 i/o - - - - - u12 p125 u2 649 i/o - - - - - w13 p124 t2 652 gnd - - - p143 gnd* gnd* - gnd* - i/o - - - - - x13 p123 t1 655 i/o - - - - m19 v12 p122 r4 658 i/o - p124 t11 p144 m20 w12 p121 r3 661 i/o - p125 u11 p145 l19 t11 p120 r2 664 i/o p96 p126 v11 p146 l18 x12 p119 r1 667 i/o p97 p127 v10 p147 l20 u11 p118 p3 670 i/o (d4) p98 p128 u10 p148 k20 v11 p117 p2 673 i/o p99 p129 t10 p149 k19 w11 p116 p1 676 vcc p100 p130 vcc* p150 vcc* vcc* p115 vcc* - gnd p101 p131 gnd* p151 gnd* gnd* p114 gnd* - i/o (d3) p102 p132 t9 p152 k18 w10 p113 n2 679 i/o ( rs) p103 p133 u9 p153 k17 v10 p112 n4 682 i/o p104 p134 v9 p154 j20 t10 p111 n3 685 i/o p105 p135 v8 p155 j19 u10 p110 m1 688 i/o - p136 u8 p156 j18 x9 p109 m2 691 i/o - p137 t8 p157 j17 w9 p108 m3 694 i/o - - - - h20 x8 p107 m4 697 xc4025e, xc4028** ex/xl pad name hq 160?? hq 208? pg 223? hq 240 bg 256?? pg 299 hq 304 bg 352? bndry scan
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-133 xc4000e and xc4000x series field programmable gate arrays * pads labelled gnd* or vcc* are internally bonded to ground or vcc planes within the associated package. they have no direct connection to any specific package pin. ** xc4028xl in the bg256 package has 16 extra gnd balls in cen- ter of package. ? = e only ?? = xl only ? = ex, xl only additional xc4025e, xc4028ex/xl package pins note: these pins may be not connected for this device revision, however for compatability with other devices in this package, these pins should be tied to gnd. i/o - - - - - v9 p106 l1 700 gnd - - - p158 gnd* gnd* - gnd* - i/o - - - - - u9 p105 l2 703 i/o - - - - - t9 p104 l3 706 i/o (d2) p106 p138 v7 p159 h19 w8 p103 j1 709 i/o p107 p139 u7 p160 h18 x7 p102 k3 712 vcc - - vcc* p161 vcc* vcc* p101 vcc* - i/o p108 p140 v6 p162 g19 v8 p99 j2 715 i/o p109 p141 u6 p163 f20 w7 p98 j3 718 i/o - - r8 p164 g18 u8 p97 k4 721 i/o - - r7 p165 f19 w6 p96 g1 724 gnd p110 p142 gnd* p166 gnd* gnd* p95 gnd* - i/o - - - - - t8 p94 h2 727 i/o - - - - - v7 p93 h3 730 i/o - - r6 p167 f18 x4 p92 j4 733 i/o - - r5 p168 e19 u7 p91 f1 736 i/o - p143 v5 p169 d20 w5 p90 g2 739 i/o - p144 v4 p170 e18 v6 p89 g3 742 i/o p111 p145 u5 p171 d19 t7 p88 f2 745 i/o p112 p146 t6 p172 c20 x3 p87 e2 748 gnd - - - - gnd* gnd* - gnd* - vcc - - - - vcc* vcc* - vcc* - i/o (d1) p113 p147 v3 p173 e17 u6 p86 f3 751 i/o ( rclk, rdy/ b us y) p114 p148 v2 p174 d18 v5 p85 g4 754 i/o - - - - - w4 p84 d2 757 i/o - - - - - w3 p83 f4 760 i/o p115 p149 u4 p175 c19 t6 p82 e3 763 i/o p116 p150 t5 p176 b20 u5 p81 c2 766 i/o (d0, din) p117 p151 u3 p177 c18 v4 p80 d3 769 i/o, sgck4 ?, gck6 ? (dout) p118 p152 t4 p178 b19 x1 p79 e4 772 cclk p119 p153 v1 p179 a20 v3 p78 c3 - vcc p120 p154 vcc* p180 vcc* vcc* p77 vcc* - o, tdo p121 p159 u2 p181 a19 u4 p76 d4 0 gnd p122 p160 gnd* p182 gnd* gnd* p75 gnd* - i/o (a0, ws) p123 p161 t3 p183 b18 w2 p74 b3 2 i/o, pgck4 ?, gck7 ? (a1) p124 p162 u1 p184 b17 v2 p73 c4 5 i/o p125 p163 p3 p185 c17 r5 p72 d5 8 i/o p126 p164 r2 p186 d16 t4 p71 a3 11 i/o (cs1, a2) p127 p165 t2 p187 a18 u3 p70 d6 14 i/o (a3) p128 p166 n3 p188 a17 v1 p69 c6 17 i/o - - - - - r4 p68 b5 20 i/o - - - - - p5 p67 a4 23 vcc - - - - vcc* vcc* - vcc* - gnd - - - - gnd* gnd* - gnd* - i/o - - p4 p189 c16 u2 p66 c7 26 i/o - - n4 p190 b16 t3 p65 b6 29 i/o p129 p167 p2 p191 a16 u1 p64 a6 32 i/o p130 p168 t1 p192 c15 p4 p63 d8 35 i/o - p169 r1 p193 b15 r3 p62 b7 38 i/o - p170 n2 p194 a15 n5 p61 a7 41 i/o - - - p195 - t2 p60 d9 44 i/o - - - - - r2 p59 c9 47 gnd p131 p171 gnd* p196 gnd* gnd* p58 gnd* - i/o p132 p172 p1 p197 b14 n4 p57 b8 50 i/o p133 p173 n1 p198 a14 p3 p56 d10 53 i/o - - m4 p199 c13 p2 p55 c10 56 i/o - - l4 p200 b13 n3 p54 b9 59 vcc - - vcc* p201 vcc* vcc* p52 vcc* - xc4025e, xc4028** ex/xl pad name hq 160?? hq 208? pg 223? hq 240 bg 256?? pg 299 hq 304 bg 352? bndry scan i/o - - - - a13 m5 p51 a9 62 i/o - - - - d12 p1 p50 d11 65 i/o - - - - - m4 p49 b11 68 i/o - - - - - n2 p48 a11 71 gnd - - - - gnd* gnd* - gnd* - i/o (a4) p134 p174 m2 p202 c12 n1 p47 d12 74 i/o (a5) p135 p175 m1 p203 b12 m3 p46 c12 77 i/o - p176 l3 p205 a12 m2 p45 b12 80 i/o p136 p177 l2 p206 b11 l5 p44 a12 83 i/o (a21) ? p137 p178 l1 p207 c11 m1 p43 c13 86 i/o (a20) ? p138 p179 k1 p208 a11 l4 p42 b13 89 i/o (a6) p139 p180 k2 p209 a10 l3 p41 a13 92 i/o (a7) p140 p181 k3 p210 b10 l2 p40 b14 95 gnd p141 p182 gnd* p211 gnd* gnd* p39 gnd* - 6/19/97 hq208 not connected pins p1 p52 p102 p107 p157 p207 p3 p53 p104 p155 p158 p208 p51 p54 p105 p156 p206 5/9/97 pg223 vcc pins d3 d10 d16 j4 j15 r4 r10 r15 gnd pins c7 c12 d4 d9 d15 g3 g16 k4 k15 m3 m16 r3 r9 r16 t7 t12 5/9/97 hq240 gnd pins p204 p219 5/9/97 xc4025e, xc4028** ex/xl pad name hq 160?? hq 208? pg 223? hq 240 bg 256?? pg 299 hq 304 bg 352? bndry scan
r xc4000e and xc4000x series field programmable gate arrays 6-134 ds006 (v. 1.7) october 4, 1999 - product speci?cation note: in xc4025 (no extension) devices in the hq304 package, p101 is a no connect (n.c.) pin. p101 is vcc in xc4025e and xc4028ex/xl devices. where necessary for compatibility, this pin can be left unconnected. xc4036ex/xldevice pinout tables the following table may contain pinout information for unsupported device/package combinations. please see the availability charts elsewhere in the xc4000 series data sheet for availability information. bg256 vcc pins c14 d6 d7 d11 d14 d15 e20 f1 f4 f17 g4 g17 k4 l17 p4 p17 p19 r2 r4 r17 u6 u7 u10 u14 u15 v7 w20 - gnd pins a1 b7 d4 d8 d13 d17 g20 h4 h17 n3 n4 n17 u4 u8 u13 u17 w14 - - - 5/9/97 pg299 vcc pins a2 a6 a11 a16 b20 e1 e5 f20 k1 l20 r1 t16 t20 w1 x5 x10 x15 x19 - - gnd pins a5 a10 a15 a19 b1 e16 e20 f1 k20 l1 r20 t1 t5 w20 x2 x6 x11 x16 - - 6/18/97 hq304 not connected pins p11 p53 p128 p205 p281 p24 p100 p176 p254 - 5/15/97 bg352 vcc pins a10 a17 b2 b25 d7 d13 d19 g23 h4 k1 k26 n23 p4 u1 u26 w23 y4 ac8 ac14 ac20 ae2 ae25 af10 af17 gnd pins a1 a2 a5 a8 a14 a19 a22 a25 a26 b1 b26 e1 e26 h1 h26 n1 p26 w1 w26 ab1 ab26 ae1 ae26 af1 af2 af5 af8 af13 af19 af22 af25 af26 ---- not connected pins a18 a24 b4 b10 b23 c1 c5 c8 c11 d1 d16 d25 f23 j26 k2 l4 l23 t3 t4 t24 u25 ab3 ac2 ac6 ac11 ac16 ac21 ac25 ad16 ad21 ad26 ae4 ae10 - - - 5/9/97 xc4036ex/xl pad name pq 160?? hq 208?? hq 240 hq 304 bg 352 pg 411 bg 432 bndry scan vcc p142 p183 p212 p38 vcc* vcc* vcc* - i/o (a8) p143 p184 p213 p37 d14 w3 d17 110 i/o (a9) p144 p185 p214 p36 c14 y2 a17 113 i/o (a19) p145 p186 p215 p35 a15 v4 c18 116 i/o (a18) p146 p187 p216 p34 b15 t2 d18 119 i/o - p188 p217 p33 c15 u1 b18 122 i/o - p189 p218 p32 d15 v6 a19 125 i/o (a10) p147 p190 p220 p31 a16 u3 b19 128 i/o (a11) p148 p191 p221 p30 b16 r1 c19 131 vcc - - - - vcc* vcc* vcc* - gnd - - - - gnd* gnd* gnd* - i/o - - - p29 c16 u5 d19 134 i/o - - - p28 b17 t4 a20 137 i/o - - - - d16 p2 b20 140 i/o - - - - a18 n1 c20 143 i/o - - - p27 c17 r5 c21 146 i/o - - - p26 b18 m2 a22 149 vcc - - p222 p25 vcc* vcc* vcc* - i/o - - p223 p23 c18 l3 b22 152 i/o - - p224 p22 d17 t6 c22 155 i/o p149 p192 p225 p21 a20 n5 b23 158 i/o p150 p193 p226 p20 b19 m4 a24 161 gnd p151 p194 p227 p19 gnd* gnd* gnd* - i/o - - - p18 c19 k2 d22 164 i/o - - - p17 d18 k4 c23 167 i/o - p195 p228 p16 a21 p6 b24 170 i/o - p196 p229 p15 b20 m6 c24 173 i/o p152 p197 p230 p14 c20 j3 a26 176 i/o p153 p198 p231 p13 b21 h2 c25 179 i/o (a12) p154 p199 p232 p12 b22 h4 d24 182 i/o (a13) p155 p200 p233 p10 c21 g3 b26 185 gnd - - - - gnd* gnd* gnd* - vcc - - - - vcc* vcc* vcc* - i/o - - - p9 d20 k6 a27 188 i/o - - - p8 a23 g1 d25 191 i/o - - - - a24 e1 c26 194 i/o - - - - b23 e3 b27 197 i/o - - p234 p7 d21 j7 c27 200 i/o - - p235 p6 c22 h6 b28 203 i/o p156 p201 p236 p5 b24 c3 d27 206 i/o p157 p202 p237 p4 c23 d2 b29 209 i/o (a14) p158 p203 p238 p3 d22 e5 c28 212 i/o, gck8 (a15) p159 p204 p239 p2 c24 g7 d28 215 vcc p160 p205 p240 p1 vcc* vcc* vcc* - gnd p1 p2 p1 p304 gnd* gnd* gnd* - i/o, gck1 (a16) p2 p4 p2 p303 d23 h8 d29 218 i/o (a17) p3 p5 p3 p302 c25 f6 c30 221 i/o p4 p6 p4 p301 d24 b4 e28 224 i/o p5 p7 p5 p300 e23 d4 e29 227 i/o, tdi p6 p8 p6 p299 c26 b2 d30 230 i/o, tck p7 p9 p7 p298 e24 g9 d31 233 i/o - - - - d25 f8 e30 236 i/o - - - - f23 c5 e31 239 i/o - - - p297 f24 a7 g28 242 i/o - - - p296 e25 a5 g29 245 vcc - - - - vcc* vcc* vcc* - gnd - - - - gnd* gnd* gnd* - i/o p8 p10 p8 p295 d26 b8 h28 248 i/o p9 p11 p9 p294 g24 c9 h29 251 i/o - p12 p10 p293 f25 e9 g30 254 xc4036ex/xl pad name pq 160?? hq 208?? hq 240 hq 304 bg 352 pg 411 bg 432 bndry scan
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-135 xc4000e and xc4000x series field programmable gate arrays i/o - p13 p11 p292 f26 f12 h30 257 i/o - - p12 p291 h23 d10 j28 260 i/o - - p13 p290 h24 b10 j29 263 i/o - - - p289 g25 f10 h31 266 i/o - - - p288 g26 f14 j30 269 gnd p10 p14 p14 p287 gnd* gnd* gnd* - i/o p11 p15 p15 p286 j23 c11 k28 272 i/o p12 p16 p16 p285 j24 b12 k29 275 i/o, tms p13 p17 p17 p284 h25 e11 k30 278 i/o p14 p18 p18 p283 k23 e15 k31 281 vcc - - p19 p282 vcc* vcc* vcc* - i/o - - p20 p280 k24 f16 l29 284 i/o - - p21 p279 j25 c13 l30 287 i/o - - - - j26 b14 m29 290 i/o - - - - l23 e17 m31 293 i/o - - - p278 l24 e13 n31 296 i/o - - - p277 k25 a15 n28 299 gnd - - p22 - gnd* gnd* gnd* - vcc - - - - vcc* vcc* vcc* - i/o - - - p276 l25 b16 p30 302 i/o - - - p275 l26 d16 p28 305 i/o - p19 p23 p274 m23 d18 p29 308 i/o - p20 p24 p273 m24 a17 r31 311 i/o p15 p21 p25 p272 m25 e19 r30 314 i/o p16 p22 p26 p271 m26 b18 r28 317 i/o p17 p23 p27 p270 n24 c17 r29 320 i/o p18 p24 p28 p269 n25 c19 t31 323 gnd p19 p25 p29 p268 gnd* gnd* gnd* - vcc p20 p26 p30 p267 vcc* vcc* vcc* - i/o p21 p27 p31 p266 n26 f20 t30 326 i/o p22 p28 p32 p265 p25 b20 t29 329 i/o p23 p29 p33 p264 p23 c21 u31 332 i/o p24 p30 p34 p263 p24 b22 u30 335 i/o - p31 p35 p262 r26 e21 u28 338 i/o - p32 p36 p261 r25 d22 u29 341 i/o - - - p260 r24 a23 v30 344 i/o - - - p259 r23 b24 v29 347 vcc - - - - vcc* vcc* vcc* - gnd - - p37 - gnd* gnd* gnd* - i/o - - - p258 t26 a25 w30 350 i/o - - - p257 t25 d24 w29 353 i/o - - - - t24 b26 y30 356 i/o - - - - u25 a27 y29 359 i/o - - p38 p256 t23 c27 y28 362 i/o - - p39 p255 v26 f24 aa30 365 vcc - - p40 p253 vcc* vcc* vcc* - i/o p25 p33 p41 p252 u24 e25 aa29 368 i/o p26 p34 p42 p251 v25 e27 ab31 371 i/o p27 p35 p43 p250 v24 b28 ab30 374 i/o p28 p36 p44 p249 u23 c29 ab29 377 gnd p29 p37 p45 p248 gnd* gnd* gnd* - i/o - - - p247 y26 f26 ab28 380 i/o - - - p246 w25 d28 ac30 383 i/o - - p46 p245 w24 b30 ac29 386 i/o - - p47 p244 v23 e29 ac28 389 i/o - p38 p48 p243 aa26 f28 ad29 392 i/o - p39 p49 p242 y25 f30 ad28 395 i/o p30 p40 p50 p241 y24 c31 ae30 398 i/o p31 p41 p51 p240 aa25 e31 ae29 401 gnd - - - - gnd* gnd* gnd* - vcc - - - - vcc* vcc* vcc* - i/o - - - p239 ab25 b32 af31 404 i/o - - - p238 aa24 a33 ae28 407 i/o p32 p42 p52 p237 y23 a35 ag31 410 i/o p33 p43 p53 p236 ac26 f32 af28 413 i/o - - - - ad26 c35 ag30 416 i/o - - - - ac25 b38 ag29 419 i/o p34 p44 p54 p235 aa23 e33 ah31 422 i/o p35 p45 p55 p234 ab24 g31 ag28 425 i/o p36 p46 p56 p233 ad25 h32 ah30 428 i/o, gck2 p37 p47 p57 p232 ac24 b36 aj30 431 o (m1) p38 p48 p58 p231 ab23 a39 ah29 434 gnd p39 p49 p59 p230 gnd* gnd* gnd* - i (m0) p40 p50 p60 p229 ad24 e35 ah28 437 vcc p41 p55 p61 p228 vcc* vcc* vcc* - xc4036ex/xl pad name pq 160?? hq 208?? hq 240 hq 304 bg 352 pg 411 bg 432 bndry scan i (m2) p42 p56 p62 p227 ac23 g33 aj28 438 i/o, gck3 p43 p57 p63 p226 ae24 d36 ak29 439 i/o (hdc) p44 p58 p64 p225 ad23 c37 ah27 442 i/o p45 p59 p65 p224 ac22 f34 ak28 445 i/o p46 p60 p66 p223 af24 j33 aj27 448 i/o p47 p61 p67 p222 ad22 d38 al28 451 i/o ( ldc) p48 p62 p68 p221 ae23 g35 ah26 454 i/o - - - - ac21 e39 al27 457 i/o - - - - ad21 k34 ah25 460 i/o - - - p220 ae22 f38 ak26 463 i/o - - - p219 af23 g37 al26 466 vcc - - - - vcc* vcc* vcc* - gnd - - - - gnd* gnd* gnd* - i/o p49 p63 p69 p218 ad20 h38 ah24 469 i/o p50 p64 p70 p217 ae21 j37 aj25 472 i/o - p65 p71 p216 af21 g39 ak25 475 i/o - p66 p72 p215 ac19 m34 aj24 478 i/o - - p73 p214 ad19 n35 al24 481 i/o - - p74 p213 ae20 p34 ah22 484 i/o - - - p212 af20 j35 aj23 487 i/o - - - p211 ac18 l37 ak23 490 gnd p51 p67 p75 p210 gnd* gnd* gnd* - i/o p52 p68 p76 p209 ad18 m38 aj22 493 i/o p53 p69 p77 p208 ae19 r35 ak22 496 i/o p54 p70 p78 p207 ac17 h36 al22 499 i/o p55 p71 p79 p206 ad17 t34 aj21 502 vcc - - p80 p204 vcc* vcc* vcc* - i/o - p72 p81 p203 ae18 n37 ah20 505 i/o - p73 p82 p202 af18 n39 ak21 508 i/o - - - - ac16 u35 ak20 511 i/o - - - - ad16 r39 aj19 514 i/o - - - p201 ae17 m36 al20 517 i/o - - - p200 ae16 v34 ah18 520 gnd - - p83 - gnd* gnd* gnd* - vcc - - - - vcc* vcc* vcc* - i/o - - - p199 af16 r37 ak19 523 i/o - - - p198 ac15 t38 aj18 526 i/o - - p84 p197 ad15 t36 al19 529 i/o - - p85 p196 ae15 v36 ak18 532 i/o p56 p74 p86 p195 af15 u37 ah17 535 i/o p57 p75 p87 p194 ad14 u39 aj17 538 i/o p58 p76 p88 p193 ae14 v38 aj16 541 i/o (init) p59 p77 p89 p192 af14 w37 ak16 544 vcc p60 p78 p90 p191 vcc* vcc* vcc* - gnd p61 p79 p91 p190 gnd* gnd* gnd* - i/o p62 p80 p92 p189 ae13 y34 al16 547 i/o p63 p81 p93 p188 ac13 ac37 ah15 550 i/o p64 p82 p94 p187 ad13 ab38 ak15 553 i/o p65 p83 p95 p186 af12 ad36 aj14 556 i/o - p84 p96 p185 ae12 aa35 ah14 559 i/o - p85 p97 p184 ad12 ae37 ak14 562 i/o - - - p183 ac12 ab36 al13 565 i/o - - - p182 af11 ad38 ak13 568 vcc - - - - vcc* vcc* vcc* - gnd - - p98 - gnd* gnd* gnd* - i/o - - - p181 ae11 ab34 aj13 571 i/o - - - p180 ad11 ae39 ah13 574 i/o - - - - ae10 am36 al12 577 i/o - - - - ac11 ac35 ak12 580 i/o - - p99 p179 af9 ag39 ah12 583 i/o - - p100 p178 ad10 ag37 aj11 586 vcc - - p101 p177 vcc* vcc* vcc* - i/o p66 p86 p102 p175 ae9 ad34 al10 589 i/o p67 p87 p103 p174 ad9 an39 ak10 592 i/o p68 p88 p104 p173 ac10 ae35 aj10 595 i/o p69 p89 p105 p172 af7 ah38 ak9 598 gnd p70 p90 p106 p171 gnd* gnd* gnd* - i/o - - - p170 ae8 aj37 al8 601 i/o - - - p169 ad8 ag35 ah10 604 i/o - - p107 p168 ac9 af34 aj9 607 i/o - - p108 p167 af6 ah36 ak8 610 i/o - p91 p109 p166 ae7 ak36 ak7 613 i/o - p92 p110 p165 ad7 am34 al6 616 i/o p71 p93 p111 p164 ae6 ah34 aj7 619 i/o p72 p94 p112 p163 ae5 aj35 ah8 622 xc4036ex/xl pad name pq 160?? hq 208?? hq 240 hq 304 bg 352 pg 411 bg 432 bndry scan
r xc4000e and xc4000x series field programmable gate arrays 6-136 ds006 (v. 1.7) october 4, 1999 - product speci?cation gnd - - - - gnd* gnd* gnd* - vcc - - - - vcc* vcc* vcc* - i/o - - - p162 ad6 al37 ak6 625 i/o - - - p161 ac7 at38 al5 628 i/o p73 p95 p113 p160 af4 am38 ah7 631 i/o p74 p96 p114 p159 af3 an37 aj6 634 i/o - - - - ae4 ak34 ak5 637 i/o - - - - ac6 ar39 al4 640 i/o p75 p97 p115 p158 ad5 an35 ak4 643 i/o p76 p98 p116 p157 ae3 al33 ah5 646 i/o p77 p99 p117 p156 ad4 av38 ak3 649 i/o, gck4 p78 p100 p118 p155 ac5 at36 aj4 652 gnd p79 p101 p119 p154 gnd* gnd* gnd* - done p80 p103 p120 p153 ad3 ar35 ah4 - vcc p81 p106 p121 p152 vcc* vcc* vcc* - program p82 p108 p122 p151 ac4 an33 ah3 - i/o (d7) p83 p109 p123 p150 ad2 am32 aj2 655 i/o, gck5 p84 p110 p124 p149 ac3 ap34 ag4 658 i/o p85 p111 p125 p148 ab4 aw39 ag3 661 i/o p86 p112 p126 p147 ad1 an31 ah2 664 i/o - - - - ab3 av36 ah1 667 i/o - - - - ac2 ar33 af4 670 i/o - - p127 p146 aa4 ap32 af3 673 i/o - - p128 p145 aa3 au35 ag2 676 i/o - - - p144 ab2 aw33 ae3 679 i/o - - - p143 ac1 au33 af2 682 vcc - - - - vcc* vcc* vcc* - gnd - - - - gnd* gnd* gnd* - i/o (d6) p87 p113 p129 p142 y3 av32 af1 685 i/o p88 p114 p130 p141 aa2 au31 ad4 688 i/o p89 p115 p131 p140 aa1 ar31 ad3 691 i/o p90 p116 p132 p139 w4 ap28 ae2 694 i/o - p117 p133 p138 w3 at32 ac3 697 i/o - p118 p134 p137 y2 av30 ad1 700 i/o - - - p136 y1 ar29 ac2 703 i/o - - - p135 v4 ap26 ab4 706 gnd p91 p119 p135 p134 gnd* gnd* gnd* - i/o - - p136 p133 v3 au29 ab3 709 i/o - - p137 p132 w2 av28 ab2 712 i/o p92 p120 p138 p131 u4 at28 ab1 715 i/o p93 p121 p139 p130 u3 ar25 aa3 718 vcc - - p140 p129 vcc* vcc* vcc* - i/o (d5) p94 p122 p141 p127 v2 ap24 aa2 721 i/o (cs0) p95 p123 p142 p126 v1 au27 y2 724 i/o - - - - t4 ar27 y4 727 i/o - - - - t3 aw27 y3 730 i/o - - - p125 u2 at24 w4 733 i/o - - - p124 t2 ar23 w3 736 gnd - - p143 - gnd* gnd* gnd* - vcc - - - - vcc* vcc* vcc* - i/o - - - p123 t1 ap22 v4 739 i/o - - - p122 r4 av24 v3 742 i/o - p124 p144 p121 r3 au23 u1 745 i/o - p125 p145 p120 r2 at22 u2 748 i/o p96 p126 p146 p119 r1 ar21 u4 751 i/o p97 p127 p147 p118 p3 av22 u3 754 i/o (d4) p98 p128 p148 p117 p2 ap20 t1 757 i/o p99 p129 p149 p116 p1 au21 t2 760 vcc p100 p130 p150 p115 vcc* vcc* vcc* - gnd p101 p131 p151 p114 gnd* gnd* gnd* - i/o (d3) p102 p132 p152 p113 n2 au19 t3 763 i/o ( rs) p103 p133 p153 p112 n4 av20 r1 766 i/o p104 p134 p154 p111 n3 av18 r2 769 i/o p105 p135 p155 p110 m1 ar19 r4 772 i/o - p136 p156 p109 m2 at18 r3 775 i/o - p137 p157 p108 m3 aw17 p2 778 i/o - - - p107 m4 av16 p3 781 i/o - - - p106 l1 ap18 p4 784 vcc - - - - vcc* vcc* vcc* - gnd - - p158 - gnd* gnd* gnd* - i/o - - - p105 l2 ar17 n3 787 i/o - - - p104 l3 at16 n4 790 i/o - - - - k2 av14 m1 793 i/o - - - - l4 aw13 m2 796 i/o (d2) p106 p138 p159 p103 j1 ar15 l2 799 xc4036ex/xl pad name pq 160?? hq 208?? hq 240 hq 304 bg 352 pg 411 bg 432 bndry scan i/o p107 p139 p160 p102 k3 ap16 l3 802 vcc - - p161 p101 vcc* vcc* vcc* - i/o p108 p140 p162 p99 j2 av12 k1 805 i/o p109 p141 p163 p98 j3 ar13 k2 808 i/o - - p164 p97 k4 au11 k3 811 i/o - - p165 p96 g1 at12 k4 814 gnd p110 p142 p166 p95 gnd* gnd* gnd* - i/o - - - p94 h2 ap14 j2 817 i/o - - - p93 h3 ar11 j3 820 i/o - - p167 p92 j4 av10 j4 823 i/o - - p168 p91 f1 at8 h1 826 i/o - p143 p169 p90 g2 at10 h2 829 i/o - p144 p170 p89 g3 ap10 h3 832 i/o p111 p145 p171 p88 f2 ap12 h4 835 i/o p112 p146 p172 p87 e2 ar9 g2 838 gnd - - - - gnd* gnd* gnd* - vcc - - - - vcc* vcc* vcc* - i/o (d1) p113 p147 p173 p86 f3 au7 g4 841 i/o (rclk, rdy/busy) p114 p148 p174 p85 g4 aw7 f2 844 i/o - - - - d1 aw5 f3 847 i/o - - - - c1 av6 e1 850 i/o - - - p84 d2 ar7 e3 853 i/o - - - p83 f4 av4 d1 856 i/o p115 p149 p175 p82 e3 an9 e4 859 i/o p116 p150 p176 p81 c2 aw1 d2 862 i/o (d0, din) p117 p151 p177 p80 d3 ap6 c2 865 i/o, gck6 (dout) p118 p152 p178 p79 e4 au3 d3 868 cclk p119 p153 p179 p78 c3 ar5 d4 - vcc p120 p154 p180 p77 vcc* vcc* vcc* - o, tdo p121 p159 p181 p76 d4 an7 c4 0 gnd p122 p160 p182 p75 gnd* gnd* gnd* - i/o (a0, ws) p123 p161 p183 p74 b3 at4 b3 2 i/o, gck7 (a1) p124 p162 p184 p73 c4 av2 d5 5 i/o p125 p163 p185 p72 d5 am8 b4 8 i/o p126 p164 p186 p71 a3 al7 c5 11 i/o - - - - c5 ar3 b5 14 i/o - - - - b4 ar1 c6 17 i/o (cs1, a2) p127 p165 p187 p70 d6 ak6 a5 20 i/o (a3) p128 p166 p188 p69 c6 an3 d7 23 i/o - - - p68 b5 am6 b6 26 i/o - - - p67 a4 am2 a6 29 vcc - - - - vcc* vcc* vcc* - gnd - - - - gnd* gnd* gnd* - i/o - - p189 p66 c7 al3 d8 32 i/o - - p190 p65 b6 ah6 c7 35 i/o p129 p167 p191 p64 a6 ap2 b7 38 i/o p130 p168 p192 p63 d8 ak4 d9 41 i/o - p169 p193 p62 b7 ag5 d10 44 i/o - p170 p194 p61 a7 af6 c9 47 i/o - - p195 p60 d9 al5 b9 50 i/o - - - p59 c9 aj3 c10 53 gnd p131 p171 p196 p58 gnd* gnd* gnd* - i/o p132 p172 p197 p57 b8 ah2 b10 56 i/o p133 p173 p198 p56 d10 ae5 a10 59 i/o - - p199 p55 c10 am4 c11 62 i/o - - p200 p54 b9 ad6 d12 65 vcc - - p201 p52 vcc* vcc* vcc* - i/o - - - p51 a9 ag3 b11 68 i/o - - - p50 d11 ag1 c12 71 i/o - - - - c11 ac5 c13 74 i/o - - - - b10 ae1 a12 77 i/o - - - p49 b11 ah4 d14 80 i/o - - - p48 a11 ab6 b13 83 gnd - - - - gnd* gnd* gnd* - vcc - - - - vcc* vcc* vcc* - i/o (a4) p134 p174 p202 p47 d12 ad2 c14 86 i/o (a5) p135 p175 p203 p46 c12 ab4 a13 89 i/o - p176 p205 p45 b12 ae3 b14 92 i/o p136 p177 p206 p44 a12 ac1 d15 95 i/o (a21) p137 p178 p207 p43 c13 ad4 c15 98 i/o (a20) p138 p179 p208 p42 b13 aa5 b15 101 i/o (a6) p139 p180 p209 p41 a13 aa3 b16 104 i/o (a7) p140 p181 p210 p40 b14 y6 a16 107 xc4036ex/xl pad name pq 160?? hq 208?? hq 240 hq 304 bg 352 pg 411 bg 432 bndry scan
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-137 xc4000e and xc4000x series field programmable gate arrays * pads labelled gnd* or vcc* are internally bonded to ground or vcc planes within the associated package. they have no direct connection to any specific package pin. ?? = xl only additional xc4036ex/xl package pins the ground (gnd) package pins in the above table should be externally connected to ground if possible; however, they can be left unconnected if necessary for compatibility with other devices. xc4044xl device pinout tables (note: xc4044xl is also available in the hq304 package. the pinout is identical to the xc4036xl in the hq304. ) gnd p141 p182 p211 p39 gnd* gnd* gnd* - 6/17/97 hq208 not connected pins p1 p3 p51 p52 p53 p54 p102 p104 p105 p107 p155 p156 p157 p158 p206 p207 p208 - - - 5/15/97 hq240 gnd pins p204 p219 - - - 6/17/97 hq304 not connected pins p11 p24 p53 p100 p128 p176 p205 p254 p281 - 5/15/97 bg352 vcc pins a10 a17 b2 b25 d7 d13 d19 g23 h4 k1 k26 n23 p4 u1 u26 w23 y4 ac8 ac14 ac20 ae2 ae25 af10 af17 gnd pins a1 a2 a5 a8 a14 a19 a22 a25 a26 b1 b26 e1 e26 h1 h26 n1 p26 w1 w26 ab1 ab26 ae1 ae26 af1 af2 af5 af8 af13 af19 af22 af25 af26 ---- not connected pins c8---- 6/16/97 xc4036ex/xl pad name pq 160?? hq 208?? hq 240 hq 304 bg 352 pg 411 bg 432 bndry scan pg411 vcc pins a3 a11 a21 a31 c39 d6 f36 j1 l39 w1 aa39 aj1 al39 ap4 at34 au1 aw9 aw19 aw29 aw37 ---- gnd pins a9 a19 a29 a37 c1 d14 d20 d26 d34 f4 j39 l1 p4 p36 w39 y4 y36 aa1 af4 af36 aj39 al1 ap36 at6 at14 at20 at26 au39 aw3 aw11 aw21 aw31 ---- not connected pins a13 b6 b34 c7 c15 c23 c25 c33 d8 d12 d30 d32 e7 e23 e37 f2 f18 f22 g5 h34 j5 k36 k38 l5 l35 n3 p38 r3 v2 w5 w35 y38 aa37 ab2 ac3 ac39 af2 af38 aj5 ak2 ak38 al35 an1 an5 ap8 ap30 ap38 ar37 at2 at30 au5 au9 au13 au15 au17 au25 au37 av8 av26 av34 aw15 aw23 aw25 aw35 - - 6/16/97 bg432 vcc pins a1 a11 a21 a31 c3 c29 d11 d21 l1 l4 l28 l31 aa1 aa4 aa28 aa31 ah11 ah21 aj3 aj29 al1 al11 al21 al31 gnd pins a2 a3 a7 a9 a14 a18 a23 a25 a29 a30 b1 b2 b30 b31 c1 c31 d16 g1 g31 j1 j31 p1 p31 t4 t28 v1 v31 ac1 ac31 ae1 ae31 ah16 aj1 aj31 ak1 ak2 ak30 ak31 al2 al3 al7 al9 al14 al18 al23 al25 al29 al30 not connected pins a4 a8 a15 a28 b8 b12 b17 b21 b25 c8 c16 c17 d6 d13 d20 d23 d26 e2 f1 f4 f28 f29 f30 f31 g3 m3 m4 m28 m30 n1 n2 n29 n30 v2 v28 w1 w2 w28 w31 y1 y31 ac4 ad2 ad30 ad31 ae4 af29 af30 ag1 ah6 ah9 ah19 ah23 aj5 aj8 aj12 aj15 aj20 aj26 ak11 ak17 ak24 ak27 al15 al17 - 5/15/97 xc4044xl pad name hq 160 hq 208 hq 240 bg 352 pg 411 bg 432 vcc p142 p183 p212 vcc* vcc* vcc* i/o (a8) p143 p184 p213 d14 w3 d17 i/o (a9) p144 p185 p214 c14 y2 a17 i/o - - - - v2 c17 i/o - - - - w5 b17 i/o (a19) p145 p186 p215 a15 v4 c18 i/o (a18) p146 p187 p216 b15 t2 d18 i/o - p188 p217 c15 u1 b18 i/o - p189 p218 d15 v6 a19 i/o (a10) p147 p190 p220 a16 u3 b19 i/o (a11) p148 p191 p221 b16 r1 c19 vcc - - - vcc* vcc* vcc* gnd - - - gnd* gnd* gnd* i/o - - - c16 u5 d19 i/o - - - b17 t4 a20 xc4044xl pad name hq 160 hq 208 hq 240 bg 352 pg 411 bg 432
r xc4000e and xc4000x series field programmable gate arrays 6-138 ds006 (v. 1.7) october 4, 1999 - product speci?cation i/o - - - d16 p2 b20 i/o - - - a18 n1 c20 i/o - - - c17 r5 c21 i/o - - - b18 m2 a22 vcc - - p222 vcc* vcc* vcc* i/o - - p223 c18 l3 b22 i/o - - p224 d17 t6 c22 i/o p149 p192 p225 a20 n5 b23 i/o p150 p193 p226 b19 m4 a24 gnd p151 p194 p227 gnd* gnd* gnd* i/o - - - c19 k2 d22 i/o - - - d18 k4 c23 i/o - p195 p228 a21 p6 b24 i/o - p196 p229 b20 m6 c24 i/o - - - - l5 d23 i/o - - - - j5 b25 i/o p152 p197 p230 c20 j3 a26 i/o p153 p198 p231 b21 h2 c25 i/o (a12) p154 p199 p232 b22 h4 d24 i/o (a13) p155 p200 p233 c21 g3 b26 gnd - - - gnd* gnd* gnd* vcc - - - vcc* vcc* vcc* i/o - - - d20 k6 a27 i/o - - - a23 g1 d25 i/o - - - a24 e1 c26 i/o - - - b23 e3 b27 i/o - - p234 d21 j7 c27 i/o - - p235 c22 h6 b28 i/o p156 p201 p236 b24 c3 d27 i/o p157 p202 p237 c23 d2 b29 i/o (a14) p158 p203 p238 d22 e5 c28 i/o, gck8 (a15) p159 p204 p239 c24 g7 d28 vcc p160 p205 p240 vcc* vcc* vcc* gnd p1 p2 p1 gnd* gnd* gnd* i/o, gck1 (a16) p2 p4 p2 d23 h8 d29 i/o (a17) p3 p5 p3 c25 f6 c30 i/o p4 p6 p4 d24 b4 e28 i/o p5 p7 p5 e23 d4 e29 i/o, tdi p6 p8 p6 c26 b2 d30 i/o, tck p7 p9 p7 e24 g9 d31 i/o - - - d25 f8 e30 i/o - - - f23 c5 e31 i/o - - - f24 a7 g28 i/o - - - e25 a5 g29 vcc - - - vcc* vcc* vcc* gnd - - - gnd* gnd* gnd* i/o - - - - c7 f30 i/o - - - - d8 f31 i/o p8 p10 p8 d26 b8 h28 i/o p9 p11 p9 g24 c9 h29 i/o - p12 p10 f25 e9 g30 i/o - p13 p11 f26 f12 h30 i/o - - p12 h23 d10 j28 i/o - - p13 h24 b10 j29 i/o - - - g25 f10 h31 i/o - - - g26 f14 j30 gnd p10 p14 p14 gnd* gnd* gnd* i/o p11 p15 p15 j23 c11 k28 i/o p12 p16 p16 j24 b12 k29 i/o, tms p13 p17 p17 h25 e11 k30 i/o p14 p18 p18 k23 e15 k31 vcc - - p19 vcc* vcc* vcc* i/o - - p20 k24 f16 l29 i/o - - p21 j25 c13 l30 i/o - - - j26 b14 m29 i/o - - - l23 e17 m31 i/o - - - l24 e13 n31 i/o - - - k25 a15 n28 gnd - - p22 gnd* gnd* gnd* vcc - - - vcc* vcc* vcc* i/o - - - - f18 n29 i/o - - - - c15 n30 i/o - - - l25 b16 p30 i/o - - - l26 d16 p28 i/o - p19 p23 m23 d18 p29 xc4044xl pad name hq 160 hq 208 hq 240 bg 352 pg 411 bg 432 i/o - p20 p24 m24 a17 r31 i/o p15 p21 p25 m25 e19 r30 i/o p16 p22 p26 m26 b18 r28 i/o p17 p23 p27 n24 c17 r29 i/o p18 p24 p28 n25 c19 t31 gnd p19 p25 p29 gnd* gnd* gnd* vcc p20 p26 p30 vcc* vcc* vcc* i/o p21 p27 p31 n26 f20 t30 i/o p22 p28 p32 p25 b20 t29 i/o p23 p29 p33 p23 c21 u31 i/o p24 p30 p34 p24 b22 u30 i/o - p31 p35 r26 e21 u28 i/o - p32 p36 r25 d22 u29 i/o - - - r24 a23 v30 i/o - - - r23 b24 v29 i/o - - - - c23 v28 i/o - - - - f22 w31 vcc - - - vcc* vcc* vcc* gnd - - p37 gnd* gnd* gnd* i/o - - - t26 a25 w30 i/o - - - t25 d24 w29 i/o - - - t24 b26 y30 i/o - - - u25 a27 y29 i/o - - p38 t23 c27 y28 i/o - - p39 v26 f24 aa30 vcc - - p40 vcc* vcc* vcc* i/o p25 p33 p41 u24 e25 aa29 i/o p26 p34 p42 v25 e27 ab31 i/o p27 p35 p43 v24 b28 ab30 i/o p28 p36 p44 u23 c29 ab29 gnd p29 p37 p45 gnd* gnd* gnd* i/o - - - y26 f26 ab28 i/o - - - w25 d28 ac30 i/o - - p46 w24 b30 ac29 i/o - - p47 v23 e29 ac28 i/o - - - - d30 ad31 i/o - - - - d32 ad30 i/o - p38 p48 aa26 f28 ad29 i/o - p39 p49 y25 f30 ad28 i/o p30 p40 p50 y24 c31 ae30 i/o p31 p41 p51 aa25 e31 ae29 gnd - - - gnd* gnd* gnd* vcc - - - vcc* vcc* vcc* i/o - - - ab25 b32 af31 i/o - - - aa24 a33 ae28 i/o p32 p42 p52 y23 a35 ag31 i/o p33 p43 p53 ac26 f32 af28 i/o - - - ad26 c35 ag30 i/o - - - ac25 b38 ag29 i/o p34 p44 p54 aa23 e33 ah31 i/o p35 p45 p55 ab24 g31 ag28 i/o p36 p46 p56 ad25 h32 ah30 i/o, gck2 p37 p47 p57 ac24 b36 aj30 o (m1) p38 p48 p58 ab23 a39 ah29 gnd p39 p49 p59 gnd* gnd* gnd* i (m0) p40 p50 p60 ad24 e35 ah28 vcc p41 p55 p61 vcc* vcc* vcc* i (m2) p42 p56 p62 ac23 g33 aj28 i/o, gck3 p43 p57 p63 ae24 d36 ak29 i/o (hdc) p44 p58 p64 ad23 c37 ah27 i/o p45 p59 p65 ac22 f34 ak28 i/o p46 p60 p66 af24 j33 aj27 i/o p47 p61 p67 ad22 d38 al28 i/o ( ldc) p48 p62 p68 ae23 g35 ah26 i/o - - - ac21 e39 al27 i/o - - - ad21 k34 ah25 i/o - - - ae22 f38 ak26 i/o - - - af23 g37 al26 vcc - - - vcc* vcc* vcc* gnd - - - gnd* gnd* gnd* i/o p49 p63 p69 ad20 h38 ah24 i/o p50 p64 p70 ae21 j37 aj25 i/o - p65 p71 af21 g39 ak25 i/o - p66 p72 ac19 m34 aj24 i/o - - - - k36 ah23 xc4044xl pad name hq 160 hq 208 hq 240 bg 352 pg 411 bg 432
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-139 xc4000e and xc4000x series field programmable gate arrays i/o - - - - k38 ak24 i/o - - p73 ad19 n35 al24 i/o - - p74 ae20 p34 ah22 i/o - - - af20 j35 aj23 i/o - - - ac18 l37 ak23 gnd p51 p67 p75 gnd* gnd* gnd* i/o p52 p68 p76 ad18 m38 aj22 i/o p53 p69 p77 ae19 r35 ak22 i/o p54 p70 p78 ac17 h36 al22 i/o p55 p71 p79 ad17 t34 aj21 vcc - - p80 vcc* vcc* vcc* i/o - p72 p81 ae18 n37 ah20 i/o - p73 p82 af18 n39 ak21 i/o - - - ac16 u35 ak20 i/o - - - ad16 r39 aj19 i/o - - - ae17 m36 al20 i/o - - - ae16 v34 ah18 gnd - - p83 gnd* gnd* gnd* vcc - - - vcc* vcc* vcc* i/o - - - af16 r37 ak19 i/o - - - ac15 t38 aj18 i/o - - p84 ad15 t36 al19 i/o - - p85 ae15 v36 ak18 i/o p56 p74 p86 af15 u37 ah17 i/o p57 p75 p87 ad14 u39 aj17 i/o - - - - w35 ak17 i/o - - - - ac39 al17 i/o p58 p76 p88 ae14 v38 aj16 i/o (init) p59 p77 p89 af14 w37 ak16 vcc p60 p78 p90 vcc* vcc* vcc* gnd p61 p79 p91 gnd* gnd* gnd* i/o p62 p80 p92 ae13 y34 al16 i/o p63 p81 p93 ac13 ac37 ah15 i/o - - - - y38 al15 i/o - - - - aa37 aj15 i/o p64 p82 p94 ad13 ab38 ak15 i/o p65 p83 p95 af12 ad36 aj14 i/o - p84 p96 ae12 aa35 ah14 i/o - p85 p97 ad12 ae37 ak14 i/o - - - ac12 ab36 al13 i/o - - - af11 ad38 ak13 vcc - - - vcc* vcc* vcc* gnd - - p98 gnd* gnd* gnd* i/o - - - ae11 ab34 aj13 i/o - - - ad11 ae39 ah13 i/o - - - ae10 am36 al12 i/o - - - ac11 ac35 ak12 i/o - - p99 af9 ag39 ah12 i/o - - p100 ad10 ag37 aj11 vcc - - p101 vcc* vcc* vcc* i/o p66 p86 p102 ae9 ad34 al10 i/o p67 p87 p103 ad9 an39 ak10 i/o p68 p88 p104 ac10 ae35 aj10 i/o p69 p89 p105 af7 ah38 ak9 gnd p70 p90 p106 gnd* gnd* gnd* i/o - - - ae8 aj37 al8 i/o - - - ad8 ag35 ah10 i/o - - p107 ac9 af34 aj9 i/o - - p108 af6 ah36 ak8 i/o - - - - ak38 aj8 i/o - - - - ap38 ah9 i/o - p91 p109 ae7 ak36 ak7 i/o - p92 p110 ad7 am34 al6 i/o p71 p93 p111 ae6 ah34 aj7 i/o p72 p94 p112 ae5 aj35 ah8 gnd - - - gnd* gnd* gnd* vcc - - - vcc* vcc* vcc* i/o - - - ad6 al37 ak6 i/o - - - ac7 at38 al5 i/o p73 p95 p113 af4 am38 ah7 i/o p74 p96 p114 af3 an37 aj6 i/o - - - ae4 ak34 ak5 i/o - - - ac6 ar39 al4 i/o p75 p97 p115 ad5 an35 ak4 i/o p76 p98 p116 ae3 al33 ah5 xc4044xl pad name hq 160 hq 208 hq 240 bg 352 pg 411 bg 432 i/o p77 p99 p117 ad4 av38 ak3 i/o, gck4 p78 p100 p118 ac5 at36 aj4 gnd p79 p101 p119 gnd* gnd* gnd* done p80 p103 p120 ad3 ar35 ah4 vcc p81 p106 p121 vcc* vcc* vcc* program p82 p108 p122 ac4 an33 ah3 i/o (d7) p83 p109 p123 ad2 am32 aj2 i/o, gck5 p84 p110 p124 ac3 ap34 ag4 i/o p85 p111 p125 ab4 aw39 ag3 i/o p86 p112 p126 ad1 an31 ah2 i/o - - - ab3 av36 ah1 i/o - - - ac2 ar33 af4 i/o - - p127 aa4 ap32 af3 i/o - - p128 aa3 au35 ag2 i/o - - - ab2 aw33 ae3 i/o - - - ac1 au33 af2 vcc - - - vcc* vcc* vcc* gnd - - - gnd* gnd* gnd* i/o (d6) p87 p113 p129 y3 av32 af1 i/o p88 p114 p130 aa2 au31 ad4 i/o p89 p115 p131 aa1 ar31 ad3 i/o p90 p116 p132 w4 ap28 ae2 i/o - - - - ap30 ad2 i/o - - - - at30 ac4 i/o - p117 p133 w3 at32 ac3 i/o - p118 p134 y2 av30 ad1 i/o - - - y1 ar29 ac2 i/o - - - v4 ap26 ab4 gnd p91 p119 p135 gnd* gnd* gnd* i/o - - p136 v3 au29 ab3 i/o - - p137 w2 av28 ab2 i/o p92 p120 p138 u4 at28 ab1 i/o p93 p121 p139 u3 ar25 aa3 vcc - - p140 vcc* vcc* vcc* i/o (d5) p94 p122 p141 v2 ap24 aa2 i/o (cs0) p95 p123 p142 v1 au27 y2 i/o - - - t4 ar27 y4 i/o - - - t3 aw27 y3 i/o - - - u2 at24 w4 i/o - - - t2 ar23 w3 gnd - - p143 gnd* gnd* gnd* vcc - - - vcc* vcc* vcc* i/o - - - - aw25 w2 i/o - - - - aw23 v2 i/o - - - t1 ap22 v4 i/o - - - r4 av24 v3 i/o - p124 p144 r3 au23 u1 i/o - p125 p145 r2 at22 u2 i/o p96 p126 p146 r1 ar21 u4 i/o p97 p127 p147 p3 av22 u3 i/o (d4) p98 p128 p148 p2 ap20 t1 i/o p99 p129 p149 p1 au21 t2 vcc p100 p130 p150 vcc* vcc* vcc* gnd p101 p131 p151 gnd* gnd* gnd* i/o (d3) p102 p132 p152 n2 au19 t3 i/o ( rs) p103 p133 p153 n4 av20 r1 i/o p104 p134 p154 n3 av18 r2 i/o p105 p135 p155 m1 ar19 r4 i/o - p136 p156 m2 at18 r3 i/o - p137 p157 m3 aw17 p2 i/o - - - m4 av16 p3 i/o - - - l1 ap18 p4 i/o - - - - au17 n1 i/o - - - - aw15 n2 vcc - - - vcc* vcc* vcc* gnd - - p158 gnd* gnd* gnd* i/o - - - l2 ar17 n3 i/o - - - l3 at16 n4 i/o - - - k2 av14 m1 i/o - - - l4 aw13 m2 i/o (d2) p106 p138 p159 j1 ar15 l2 i/o p107 p139 p160 k3 ap16 l3 vcc - - p161 vcc* vcc* vcc* i/o p108 p140 p162 j2 av12 k1 i/o p109 p141 p163 j3 ar13 k2 xc4044xl pad name hq 160 hq 208 hq 240 bg 352 pg 411 bg 432
r xc4000e and xc4000x series field programmable gate arrays 6-140 ds006 (v. 1.7) october 4, 1999 - product speci?cation * pads labelled gnd* or vcc* are internally bonded to ground or vcc planes within the associated package. they have no direct connection to any specific package pin. additional xc4044xl package pins note: these pins may be not connected for this device revision, however for compatability with other devices in this package, these pins should be tied to gnd. i/o - - p164 k4 au11 k3 i/o - - p165 g1 at12 k4 gnd p110 p142 p166 gnd* gnd* gnd* i/o - - - h2 ap14 j2 i/o - - - h3 ar11 j3 i/o - - p167 j4 av10 j4 i/o - - p168 f1 at8 h1 i/o - p143 p169 g2 at10 h2 i/o - p144 p170 g3 ap10 h3 i/o p111 p145 p171 f2 ap12 h4 i/o p112 p146 p172 e2 ar9 g2 i/o - - - - au9 g3 i/o - - - - av8 f1 gnd - - - gnd* gnd* gnd* vcc - - - vcc* vcc* vcc* i/o (d1) p113 p147 p173 f3 au7 g4 i/o (rclk, rdy/busy) p114 p148 p174 g4 aw7 f2 i/o - - - d1 aw5 f3 i/o - - - c1 av6 e1 i/o - - - d2 ar7 e3 i/o - - - f4 av4 d1 i/o p115 p149 p175 e3 an9 e4 i/o p116 p150 p176 c2 aw1 d2 i/o (d0, din) p117 p151 p177 d3 ap6 c2 i/o, gck6 (dout) p118 p152 p178 e4 au3 d3 cclk p119 p153 p179 c3 ar5 d4 vcc p120 p154 p180 vcc* vcc* vcc* o, tdo p121 p159 p181 d4 an7 c4 gnd p122 p160 p182 gnd* gnd* gnd* i/o (a0, ws) p123 p161 p183 b3 at4 b3 i/o, gck7 (a1) p124 p162 p184 c4 av2 d5 i/o p125 p163 p185 d5 am8 b4 i/o p126 p164 p186 a3 al7 c5 i/o - - - c5 ar3 b5 i/o - - - b4 ar1 c6 i/o (cs1,a2) p127 p165 p187 d6 ak6 a5 i/o (a3) p128 p166 p188 c6 an3 d7 i/o - - - b5 am6 b6 i/o - - - a4 am2 a6 vcc - - - vcc* vcc* vcc* gnd - - - gnd* gnd* gnd* i/o - - p189 c7 al3 d8 i/o - - p190 b6 ah6 c7 i/o p129 p167 p191 a6 ap2 b7 i/o p130 p168 p192 d8 ak4 d9 i/o - - - c8 an1 b8 i/o - - - - ak2 a8 i/o - p169 p193 b7 ag5 d10 i/o - p170 p194 a7 af6 c9 i/o - - p195 d9 al5 b9 i/o - - - c9 aj3 c10 gnd p131 p171 p196 gnd* gnd* gnd* i/o p132 p172 p197 b8 ah2 b10 i/o p133 p173 p198 d10 ae5 a10 i/o - - p199 c10 am4 c11 i/o - - p200 b9 ad6 d12 vcc - - p201 vcc* vcc* vcc* i/o - - - a9 ag3 b11 i/o - - - d11 ag1 c12 i/o - - - c11 ac5 c13 i/o - - - b10 ae1 a12 i/o - - - b11 ah4 d14 i/o - - - a11 ab6 b13 gnd - - - gnd* gnd* gnd* vcc - - - vcc* vcc* vcc* i/o (a4) p134 p174 p202 d12 ad2 c14 i/o (a5) p135 p175 p203 c12 ab4 a13 i/o - p176 p205 b12 ae3 b14 i/o p136 p177 p206 a12 ac1 d15 i/o (a21) p137 p178 p207 c13 ad4 c15 i/o (a20) p138 p179 p208 b13 aa5 b15 i/o - - - - ab2 a15 i/o - - - - ac3 c16 i/o (a6) p139 p180 p209 a13 aa3 b16 i/o (a7) p140 p181 p210 b14 y6 a16 xc4044xl pad name hq 160 hq 208 hq 240 bg 352 pg 411 bg 432 gnd p141 p182 p211 gnd* gnd* gnd* 6/18//97 hq208 not connected pins p1 p3 p51 p52 p53 p54 p102 p104 p105 p107 p155 p156 p157 p158 p206 p207 p208 - - - - 5/29/97 hq240 gnd pins p204 p219 - - - - - 5/29/97 bg352 vcc pins a10 a17 b2 b25 d7 d13 d19 g23 h4 k1 k26 n23 p4 u1 u26 w23 y4 ac8 ac14 ac20 ae2 ae25 af10 af17 - - - - gnd pins a1 a2 a5 a8 a14 a19 a22 a25 a26 b1 b26 e1 e26 h1 h26 n1 p26 w1 w26 ab1 ab26 ae1 ae26 af1 af2 af5 af8 af13 af19 af22 af25 af26 - - - 6/13/97 pg411 vcc pins a3 a11 a21 a31 c39 d6 f36 j1 l39 w1 aa39 aj1 al39 ap4 at34 au1 aw9 aw19 aw29 aw37 - gnd pins a9 a19 a29 a37 c1 d14 d20 d26 d34 f4 j39 l1 p4 p36 w39 y4 y36 aa1 af4 af36 aj39 al1 ap36 at6 at14 at20 at26 au39 aw3 aw11 aw21 aw31 - - - not connected pins a13 b6 b34 c25 c33 d12 e7 e23 e37 f2 g5 h34 l35 n3 p38 r3 af2 af38 aj5 al35 an5 ap8 ar37 at2 au5 au13 au15 au25 au37 av26 av34 aw35 - - - 6/2/97 xc4044xl pad name hq 160 hq 208 hq 240 bg 352 pg 411 bg 432
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-141 xc4000e and xc4000x series field programmable gate arrays xc4052xl device pinout tables (note: xc4052xl is also available in the hq304 package. the pinout is identical to the xc4036xl in hq304.) bg432 vcc pins a1 a11 a21 a31 c3 c29 d11 d21 l1 l4 l28 l31 aa1 aa4 aa28 aa31 ah11 ah21 aj3 aj29 al1 al11 al21 al31 - - - - gnd pins a2 a3 a7 a9 a14 a18 a23 a25 a29 a30 b1 b2 b30 b31 c1 c31 d16 g1 g31 j1 j31 p1 p31 t4 t28 v1 v31 ac1 ac31 ae1 ae31 ah16 aj1 aj31 ak1 ak2 ak30 ak31 al2 al3 al7 al9 al14 al18 al23 al25 al29 al30 - not connected pins a4 a28 b12 b21 c8 d6 d13 d20 d26 e2 f4 f28 f29 m3 m4 m28 m30 w1 w28 y1 y31 ae4 af29 af30 ag1 ah6 ah19 aj5 aj12 aj20 aj26 ak11 ak27 - - 5/29/97 xc4052xl pad name hq 240 pg 411 bg 432 bg 560 vcc p212 vcc* vcc* vcc* i/o (a8) p213 w3 d17 a17 i/o (a9) p214 y2 a17 b18 i/o - v2 c17 c18 i/o - w5 b17 e18 gnd - gnd* gnd* gnd* i/o (a19) p215 v4 c18 c19 i/o (a18) p216 t2 d18 d19 i/o p217 u1 b18 e19 i/o p218 v6 a19 b20 i/o (a10) p220 u3 b19 c20 i/o (a11) p221 r1 c19 d20 vcc - vcc* vcc* vcc* gnd - gnd* gnd* gnd* i/o - u5 d19 a21 i/o - t4 a20 e20 i/o - p2 b20 b21 i/o - n1 c20 c21 i/o - r3 b21 d21 i/o - n3 d20 b22 gnd - gnd* gnd* gnd* i/o - r5 c21 c23 i/o - m2 a22 e22 vcc p222 vcc* vcc* vcc* i/o p223 l3 b22 b24 i/o p224 t6 c22 d23 i/o p225 n5 b23 c24 i/o p226 m4 a24 a25 gnd p227 gnd* gnd* gnd* i/o - k2 d22 e23 i/o - k4 c23 b25 i/o p228 p6 b24 d24 i/o p229 m6 c24 c25 gnd - gnd* gnd* gnd* i/o - l5 d23 e25 i/o - j5 b25 c27 i/o p230 j3 a26 d26 i/o p231 h2 c25 b28 i/o (a12) p232 h4 d24 b29 i/o (a13) p233 g3 b26 e26 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - k6 a27 c28 i/o - g1 d25 d27 i/o - e1 c26 b30 i/o - e3 b27 c29 i/o - f2 a28 e27 i/o - g5 d26 a31 gnd - gnd* gnd* gnd* i/o p234 j7 c27 d28 i/o p235 h6 b28 c30 i/o p236 c3 d27 d29 i/o p237 d2 b29 e28 i/o (a14) p238 e5 c28 d30 i/o, gck8 (a15) p239 g7 d28 e29 vcc p240 vcc* vcc* vcc* gnd p1 gnd* gnd* gnd* i/o, gck1 (a16) p2 h8 d29 b33 i/o (a17) p3 f6 c30 f29 i/o p4 b4 e28 e30 i/o p5 d4 e29 d31 i/o, tdi p6 b2 d30 f30 i/o, tck p7 g9 d31 c33 gnd - gnd* gnd* gnd* i/o - e7 f28 g29 i/o - b6 f29 e31 i/o - f8 e30 d32 i/o - c5 e31 g30 i/o - a7 g28 f31 i/o - a5 g29 h29 vcc - vcc* vcc* vcc* gnd - gnd* gnd* gnd* i/o - c7 f30 h30 i/o - d8 f31 g31 i/o p8 b8 h28 j29 i/o p9 c9 h29 f33 i/o p10 e9 g30 g32 i/o p11 f12 h30 j30 gnd - gnd* gnd* gnd* i/o p12 d10 j28 k30 i/o p13 b10 j29 h33 i/o - f10 h31 l29 i/o - f14 j30 k31 gnd p14 gnd* gnd* gnd* i/o p15 c11 k28 l30 xc4052xl pad name hq 240 pg 411 bg 432 bg 560
r xc4000e and xc4000x series field programmable gate arrays 6-142 ds006 (v. 1.7) october 4, 1999 - product speci?cation i/o p16 b12 k29 k32 i/o, tms p17 e11 k30 j33 i/o p18 e15 k31 m29 vcc p19 vcc* vcc* vcc* i/o p20 f16 l29 l32 i/o p21 c13 l30 m31 gnd - gnd* gnd* gnd* i/o - a13 m30 n29 i/o - d12 m28 l33 i/o - b14 m29 m32 i/o - e17 m31 p29 i/o - e13 n31 p30 i/o - a15 n28 n33 gnd p22 gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - f18 n29 p31 i/o - c15 n30 p32 i/o - b16 p30 r29 i/o - d16 p28 r30 i/o p23 d18 p29 r31 i/o p24 a17 r31 r33 gnd - gnd* gnd* gnd* i/o p25 e19 r30 t31 i/o p26 b18 r28 t29 i/o p27 c17 r29 u32 i/o p28 c19 t31 u31 gnd p29 gnd* gnd* gnd* vcc p30 vcc* vcc* vcc* i/o p31 f20 t30 u29 i/o p32 b20 t29 u30 i/o p33 c21 u31 v31 i/o p34 b22 u30 v29 gnd - gnd* gnd* gnd* i/o p35 e21 u28 v30 i/o p36 d22 u29 w33 i/o - a23 v30 w31 i/o - b24 v29 w30 i/o - c23 v28 w29 i/o - f22 w31 y32 vcc - vcc* vcc* vcc* gnd p37 gnd* gnd* gnd* i/o - a25 w30 y31 i/o - d24 w29 y30 i/o - e23 w28 aa32 i/o - c25 y31 aa31 i/o - b26 y30 aa30 i/o - a27 y29 ab32 gnd - gnd* gnd* gnd* i/o p38 c27 y28 aa29 i/o p39 f24 aa30 ab31 vcc p40 vcc* vcc* vcc* i/o p41 e25 aa29 ac31 i/o p42 e27 ab31 ab29 i/o p43 b28 ab30 ad32 i/o p44 c29 ab29 ac30 gnd p45 gnd* gnd* gnd* i/o - f26 ab28 ad31 i/o - d28 ac30 ae33 i/o p46 b30 ac29 ac29 i/o p47 e29 ac28 ae32 gnd - gnd* gnd* gnd* i/o - d30 ad31 ag33 i/o - d32 ad30 ah33 i/o p48 f28 ad29 ae29 i/o p49 f30 ad28 ag31 i/o p50 c31 ae30 af30 i/o p51 e31 ae29 ah32 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - b32 af31 aj32 xc4052xl pad name hq 240 pg 411 bg 432 bg 560 i/o - a33 ae28 af29 i/o - c33 af30 ah31 i/o - b34 af29 ag30 i/o p52 a35 ag31 ak32 i/o p53 f32 af28 aj31 gnd - gnd* gnd* gnd* i/o - c35 ag30 ag29 i/o - b38 ag29 al33 i/o p54 e33 ah31 ah30 i/o p55 g31 ag28 ak31 i/o p56 h32 ah30 aj30 i/o, gck2 p57 b36 aj30 ah29 o (m1) p58 a39 ah29 ak30 gnd p59 gnd* gnd* gnd* i (m0) p60 e35 ah28 aj29 vcc p61 vcc* vcc* vcc* i (m2) p62 g33 aj28 an32 i/o, gck3 p63 d36 ak29 aj28 i/o (hdc) p64 c37 ah27 ak29 i/o p65 f34 ak28 al30 i/o p66 j33 aj27 ak28 i/o p67 d38 al28 am31 i/o (ldc) p68 g35 ah26 aj27 gnd - gnd* gnd* gnd* i/o - e37 ak27 an31 i/o - h34 aj26 al29 i/o - e39 al27 ak27 i/o - k34 ah25 al28 i/o - f38 ak26 aj26 i/o - g37 al26 am30 vcc - vcc* vcc* vcc* gnd - gnd* gnd* gnd* i/o p69 h38 ah24 am29 i/o p70 j37 aj25 ak26 i/o p71 g39 ak25 al27 i/o p72 m34 aj24 aj25 i/o - k36 ah23 an29 i/o - k38 ak24 an28 gnd - gnd* gnd* gnd* i/o p73 n35 al24 al25 i/o p74 p34 ah22 aj23 i/o - j35 aj23 an26 i/o - l37 ak23 al24 gnd p75 gnd* gnd* gnd* i/o p76 m38 aj22 ak23 i/o p77 r35 ak22 an25 i/o p78 h36 al22 aj22 i/o p79 t34 aj21 al23 vcc p80 vcc* vcc* vcc* i/o p81 n37 ah20 am24 i/o p82 n39 ak21 ak22 gnd - gnd* gnd* gnd* i/o - p38 aj20 ak21 i/o - l35 ah19 am22 i/o - u35 ak20 aj20 i/o - r39 aj19 al21 i/o - m36 al20 an21 i/o - v34 ah18 ak20 gnd p83 gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - r37 ak19 al20 i/o - t38 aj18 aj19 i/o p84 t36 al19 am20 i/o p85 v36 ak18 ak19 i/o p86 u37 ah17 al19 i/o p87 u39 aj17 an19 gnd - gnd* gnd* gnd* i/o - w35 ak17 al18 i/o - ac39 al17 am18 i/o p88 v38 aj16 ak17 xc4052xl pad name hq 240 pg 411 bg 432 bg 560
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-143 xc4000e and xc4000x series field programmable gate arrays i/o (init) p89 w37 ak16 aj17 vcc p90 vcc* vcc* vcc* gnd p91 gnd* gnd* gnd* i/o p92 y34 al16 al17 i/o p93 ac37 ah15 am17 i/o - y38 al15 an17 i/o - aa37 aj15 ak16 gnd - gnd* gnd* gnd* i/o p94 ab38 ak15 am16 i/o p95 ad36 aj14 al15 i/o p96 aa35 ah14 ak15 i/o p97 ae37 ak14 aj15 i/o - ab36 al13 an15 i/o - ad38 ak13 am14 vcc - vcc* vcc* vcc* gnd p98 gnd* gnd* gnd* i/o - ab34 aj13 al14 i/o - ae39 ah13 ak14 i/o - am36 al12 aj14 i/o - ac35 ak12 an13 i/o - al35 aj12 am13 i/o - af38 ak11 al13 gnd - gnd* gnd* gnd* i/o p99 ag39 ah12 ak12 i/o p100 ag37 aj11 an11 vcc p101 vcc* vcc* vcc* i/o p102 ad34 al10 aj12 i/o p103 an39 ak10 al11 i/o p104 ae35 aj10 ak11 i/o p105 ah38 ak9 am10 gnd p106 gnd* gnd* gnd* i/o - aj37 al8 al10 i/o - ag35 ah10 aj11 i/o p107 af34 aj9 an9 i/o p108 ah36 ak8 ak10 gnd - gnd* gnd* gnd* i/o - ak38 aj8 an7 i/o - ap38 ah9 aj9 i/o p109 ak36 ak7 al7 i/o p110 am34 al6 ak8 i/o p111 ah34 aj7 an6 i/o p112 aj35 ah8 am6 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - al37 ak6 aj8 i/o - at38 al5 al6 i/o p113 am38 ah7 ak7 i/o p114 an37 aj6 am5 i/o - ak34 ak5 am4 i/o - ar39 al4 aj7 gnd - gnd* gnd* gnd* i/o - ar37 ah6 al5 i/o - au37 aj5 ak6 i/o p115 an35 ak4 an3 i/o p116 al33 ah5 ak5 i/o p117 av38 ak3 aj6 i/o, gck4 p118 at36 aj4 al4 gnd p119 gnd* gnd* gnd* done p120 ar35 ah4 aj5 vcc p121 vcc* vcc* vcc* program p122 an33 ah3 am1 i/o (d7) p123 am32 aj2 ah5 i/o, gck5 p124 ap34 ag4 aj4 i/o p125 aw39 ag3 ak3 i/o p126 an31 ah2 ah4 i/o - av36 ah1 al1 i/o - ar33 af4 ag5 gnd - gnd* gnd* gnd* i/o p127 ap32 af3 aj3 i/o p128 au35 ag2 ak2 xc4052xl pad name hq 240 pg 411 bg 432 bg 560 i/o - av34 ag1 ag4 i/o - aw35 ae4 ah3 i/o - aw33 ae3 af5 i/o - au33 af2 aj2 vcc - vcc* vcc* vcc* gnd - gnd* gnd* gnd* i/o (d6) p129 av32 af1 aj1 i/o p130 au31 ad4 af4 i/o p131 ar31 ad3 ag3 i/o p132 ap28 ae2 ae5 i/o - ap30 ad2 ah1 i/o - at30 ac4 af3 gnd - gnd* gnd* gnd* i/o p133 at32 ac3 ae3 i/o p134 av30 ad1 ac5 i/o - ar29 ac2 ae1 i/o - ap26 ab4 ad3 gnd p135 gnd* gnd* gnd* i/o p136 au29 ab3 ac4 i/o p137 av28 ab2 ad2 i/o p138 at28 ab1 ab5 i/o p139 ar25 aa3 ac3 vcc p140 vcc* vcc* vcc* i/o (d5) p141 ap24 aa2 aa5 i/o (cs0) p142 au27 y2 ab3 gnd - gnd* gnd* gnd* i/o - ar27 y4 ab2 i/o - aw27 y3 aa4 i/o - au25 y1 aa3 i/o - av26 w1 y5 i/o - at24 w4 y3 i/o - ar23 w3 y2 gnd p143 gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - aw25 w2 w5 i/o - aw23 v2 w4 i/o - ap22 v4 w3 i/o - av24 v3 w1 i/o p144 au23 u1 v3 i/o p145 at22 u2 v5 gnd - gnd* gnd* gnd* i/o p146 ar21 u4 v4 i/o p147 av22 u3 v2 i/o (d4) p148 ap20 t1 u5 i/o p149 au21 t2 u4 vcc p150 vcc* vcc* vcc* gnd p151 gnd* gnd* gnd* i/o (d3) p152 au19 t3 u3 i/o ( rs) p153 av20 r1 t2 i/o p154 av18 r2 t4 i/o p155 ar19 r4 r1 gnd - gnd* gnd* gnd* i/o p156 at18 r3 r3 i/o p157 aw17 p2 r4 i/o - av16 p3 r5 i/o - ap18 p4 p2 i/o - au17 n1 p3 i/o - aw15 n2 p4 vcc - vcc* vcc* vcc* gnd p158 gnd* gnd* gnd* i/o - ar17 n3 n1 i/o - at16 n4 p5 i/o - av14 m1 n2 i/o - aw13 m2 n3 i/o - au15 m3 n5 i/o - au13 m4 m3 gnd - gnd* gnd* gnd* i/o (d2) p159 ar15 l2 m4 i/o p160 ap16 l3 l1 vcc p161 vcc* vcc* vcc* xc4052xl pad name hq 240 pg 411 bg 432 bg 560
r xc4000e and xc4000x series field programmable gate arrays 6-144 ds006 (v. 1.7) october 4, 1999 - product speci?cation * pads labelled gnd* or vcc* are internally bonded to ground or vcc planes within the associated package. they have no direct connection to any specific package pin. additional xc4052xl package pins note: these pins may be not connected for this device revision, however for compatability with other devices in this package, these pins should be tied to gnd. i/o p162 av12 k1 k2 i/o p163 ar13 k2 l4 i/o p164 au11 k3 j1 i/o p165 at12 k4 k3 gnd p166 gnd* gnd* gnd* i/o - ap14 j2 l5 i/o - ar11 j3 j2 i/o p167 av10 j4 k4 i/o p168 at8 h1 j3 gnd - gnd* gnd* gnd* i/o p169 at10 h2 g1 i/o p170 ap10 h3 f1 i/o p171 ap12 h4 j5 i/o p172 ar9 g2 g3 i/o - au9 g3 h4 i/o - av8 f1 f2 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o (d1) p173 au7 g4 f3 i/o (rclk, rdy/busy) p174 aw7 f2 g4 i/o - aw5 f3 d2 i/o - av6 e1 e3 i/o - au5 f4 g5 i/o - ap8 e2 c1 gnd - gnd* gnd* gnd* i/o - ar7 e3 f4 i/o - av4 d1 d3 i/o p175 an9 e4 b3 i/o p176 aw1 d2 f5 i/o (d0, din) p177 ap6 c2 e4 i/o, gck6 (dout) p178 au3 d3 d4 cclk p179 ar5 d4 c4 vcc p180 vcc* vcc* vcc* o, tdo p181 an7 c4 e6 gnd p182 gnd* gnd* gnd* i/o (a0, ws) p183 at4 b3 d5 i/o, gck7 (a1) p184 av2 d5 a2 i/o p185 am8 b4 d6 i/o p186 al7 c5 a3 i/o - at2 a4 e7 i/o - an5 d6 c5 gnd - gnd* gnd* gnd* i/o - ar3 b5 b4 i/o - ar1 c6 d7 i/o (cs1, a2) p187 ak6 a5 c6 i/o (a3) p188 an3 d7 e8 i/o - am6 b6 b5 i/o - am2 a6 a5 vcc - vcc* vcc* vcc* gnd - gnd* gnd* gnd* i/o p189 al3 d8 d8 i/o p190 ah6 c7 c7 i/o p191 ap2 b7 e9 i/o p192 ak4 d9 a6 i/o - an1 b8 b7 i/o - ak2 a8 d9 gnd - gnd* gnd* gnd* i/o p193 ag5 d10 e11 i/o p194 af6 c9 a9 i/o p195 al5 b9 c10 i/o - aj3 c10 d11 gnd p196 gnd* gnd* gnd* i/o p197 ah2 b10 b10 i/o p198 ae5 a10 e12 i/o p199 am4 c11 c11 i/o p200 ad6 d12 b11 vcc p201 vcc* vcc* vcc* i/o - ag3 b11 d12 i/o - ag1 c12 a11 gnd - gnd* gnd* gnd* xc4052xl pad name hq 240 pg 411 bg 432 bg 560 i/o - af2 d13 c13 i/o - aj5 b12 e14 i/o - ac5 c13 a13 i/o - ae1 a12 d14 i/o - ah4 d14 c14 i/o - ab6 b13 b14 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o (a4) p202 ad2 c14 e15 i/o (a5) p203 ab4 a13 d15 i/o p205 ae3 b14 c15 i/o p206 ac1 d15 a15 i/o (a21) p207 ad4 c15 c16 i/o (a20) p208 aa5 b15 e16 gnd - gnd* gnd* gnd* i/o - ab2 a15 b17 i/o - ac3 c16 c17 i/o (a6) p209 aa3 b16 e17 i/o (a7) p210 y6 a16 d17 gnd p211 gnd* gnd* gnd* 6/20/97 hq240 gnd pins p204 p219 - - - - - 6/3/97 pg411 vcc pins a3 a11 a21 a31 c39 d6 f36 j1 l39 w1 aa39 aj1 al39 ap4 at34 au1 aw9 aw19 aw29 aw37 - gnd pins a9 a19 a29 a37 c1 d14 d20 d26 d34 f4 j39 li p4 p36 w39 y4 y36 aa1 af4 af36 aj39 al1 ap36 at6 at14 at20 at26 au39 aw3 aw11 aw21 aw31 - - - 6/3/97 bg432 vcc pins a1 a11 a21 a31 c3 c29 d11 d21 l1 l4 l28 l31 aa1 aa4 aa28 aa31 ah11 ah21 aj3 aj29 al1 al11 al21 al31 - - - - gnd pins a2 a3 a7 a9 a14 a18 a23 a25 a29 a30 b1 b2 b30 b31 c1 c31 d16 g1 g31 j1 j31 p1 p31 t4 t28 v1 v31 ac1 ac31 ae1 ae31 ah16 aj1 aj31 ak1 ak2 ak30 ak31 al2 al3 al7 al9 al14 al18 al23 al25 al29 al30 - not connected pins c8------ 6/3/97 xc4052xl pad name hq 240 pg 411 bg 432 bg 560
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-145 xc4000e and xc4000x series field programmable gate arrays xc4062xl device pinout tables (note: xc4062xl is also available in the hq304 package. the pinout is identical to the xc4036xl in hq304.) pg560 vcc pins a4 a10 a16 a22 a26 a30 b2 b13 b19 b32 c3 c31 c32 d1 d33 e5 h1 k33 m1 n32 r2 t33 v1 w32 aa2 ab33 ad1 af33 ak1 ak4 ak33 al2 al3 al31 am2 am15 am21 am32 an4 an8 an12 an18 an24 an30 - - - - - gnd pins a7 a12 a14 a18 a20 a24 a29 a32 b1 b6 b9 b15 b23 b27 b31 c2 e1 f32 g2 g33 j32 k1 l2 m33 p1 p33 r32 t1 v33 w2 y1 y33 ab1 ac32 ad33 ae2 ag1 ag32 ah2 aj33 al32 am3 am7 am11 am19 am25 am28 am33 an2 an5 an10 an14 an16 an20 an22 an27 not connected pins a1 a8 a19 a23 a27 a28 a33 b8 b12 b16 b26 c8 c9 c12 c22 c26 d10 d13 d16 d18 d22 d25 e2 e10 e13 e21 e24 e32 e33 h2 h3 h5 h31 h32 j4 j31 k5 k29 l3 l31 m2 m5 m30 n4 n30 n31 t3 t5 t30 t32 u1 u2 u33 v32 y4 y29 aa1 aa33 ab4 ab30 ac1 ac2 ac33 ad4 ad5 ad29 ad30 ae4 ae30 ae31 af1 af2 af31 af32 ag2 aj10 aj13 aj16 aj18 aj21 aj24 ak9 ak13 ak18 ak24 ak25 al8 al9 al12 al16 al22 al26 am8 am9 am12 am23 am26 am27 an1 an23 an33 - - - - 6/20/97 xc4062xl pad name hq240 bg432 pg475 bg560 vcc p212 vcc* vcc* vcc* i/o (a8) p213 d17 y2 a17 i/o (a9) p214 a17 y4 b18 i/o - c17 w5 c18 i/o - b17 y6 e18 i/o - - u3 d18 i/o - - w3 a19 gnd - gnd* gnd* gnd* i/o (a19) p215 c18 w1 c19 i/o (a18) p216 d18 u5 d19 i/o p217 b18 w7 e19 i/o p218 a19 u7 b20 i/o (a10) p220 b19 v2 c20 i/o (a11) p221 c19 v4 d20 vcc - vcc* vcc* vcc* gnd - gnd* gnd* gnd* i/o - d19 v6 a21 i/o - a20 r1 e20 i/o - b20 t6 b21 i/o - c20 r3 c21 i/o - b21 r5 d21 i/o - d20 t4 b22 gnd - gnd* gnd* gnd* i/o - c21 p2 c23 i/o - a22 n1 e22 vcc p222 vcc* vcc* vcc* i/o p223 b22 n3 b24 i/o p224 c22 p4 d23 i/o p225 b23 r7 c24 i/o p226 a24 m2 a25 gnd p227 gnd* gnd* gnd* i/o - d22 m4 e23 i/o - c23 l3 b25 i/o p228 b24 n5 d24 i/o p229 c24 k2 c25 i/o - - l5 b26 i/o - - j1 e24 gnd - gnd* gnd* gnd* i/o - d23 m6 e25 i/o - b25 k4 c27 i/o p230 a26 j3 d26 i/o p231 c25 j5 b28 i/o (a12) p232 d24 h2 b29 i/o (a13) p233 b26 g1 e26 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - a27 l7 c28 i/o - d25 k6 d27 i/o - c26 e1 b30 i/o - b27 h4 c29 i/o - a28 g5 e27 i/o - d26 f2 a31 gnd - gnd* gnd* gnd* i/o p234 c27 h6 d28 i/o p235 b28 c3 c30 i/o p236 d27 f4 d29 i/o p237 b29 c5 e28 xc4062xl pad name hq240 bg432 pg475 bg560
r xc4000e and xc4000x series field programmable gate arrays 6-146 ds006 (v. 1.7) october 4, 1999 - product speci?cation i/o (a14) p238 c28 e3 d30 i/o gck8 (a15) p239 d28 e5 e29 vcc p240 vcc* vcc* vcc* gnd p1 gnd* gnd* gnd* i/o, gck1 (a16) p2 d29 g7 b33 i/o (a17) p3 c30 d4 f29 i/o p4 e28 a5 e30 i/o p5 e29 b4 d31 i/o, tdi p6 d30 d6 f30 i/o, tck p7 d31 f8 c33 gnd - gnd* gnd* gnd* i/o - f28 b6 g29 i/o - f29 e7 e31 i/o - e30 d8 d32 i/o - e31 g9 g30 i/o - g28 e9 f31 i/o - g29 a7 h29 vcc - vcc* vcc* vcc* gnd - gnd* gnd* gnd* i/o - f30 b8 h30 i/o - f31 c9 g31 i/o p8 h28 g11 j29 i/o p9 h29 d10 f33 i/o p10 g30 e11 g32 i/o p11 h30 a9 j30 gnd - gnd* gnd* gnd* i/o - - b10 h32 i/o - - c11 j31 i/o p12 j28 f12 k30 i/o p13 j29 d12 h33 i/o - h31 a11 l29 i/o - j30 g15 k31 gnd p14 gnd* gnd* gnd* i/o p15 k28 b12 l30 i/o p16 k29 e13 k32 i/o, tms p17 k30 c13 j33 i/o p18 k31 a13 m29 vcc p19 vcc* vcc* vcc* i/o p20 l29 b14 l32 i/o p21 l30 c15 m31 gnd - gnd* gnd* gnd* i/o - m30 g17 n29 i/o - m28 f14 l33 i/o - m29 d16 m32 i/o - m31 d14 p29 i/o - n31 a15 p30 i/o - n28 c17 n33 gnd p22 gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - n29 d18 p31 i/o - n30 b18 p32 i/o - p30 f16 r29 i/o - p28 g19 r30 i/o p23 p29 e17 r31 i/o p24 r31 e19 r33 gnd - gnd* gnd* gnd* i/o p25 r30 a19 t31 i/o p26 r28 f18 t29 i/o - - c19 t30 i/o - - d20 t32 i/o p27 r29 f20 u32 i/o p28 t31 b20 u31 gnd p29 gnd* gnd* gnd* vcc p30 vcc* vcc* vcc* i/o p31 t30 c21 u29 i/o p32 t29 a21 u30 i/o - - d22 u33 i/o - - b22 v32 i/o p33 u31 e23 v31 i/o p34 u30 f22 v29 xc4062xl pad name hq240 bg432 pg475 bg560 gnd - gnd* gnd* gnd* i/o p35 u28 c23 v30 i/o p36 u29 f24 w33 i/o - v30 a23 w31 i/o - v29 e25 w30 i/o - v28 g23 w29 i/o - w31 b24 y32 vcc - vcc* vcc* vcc* gnd p37 gnd* gnd* gnd* i/o - w30 d24 y31 i/o - w29 c25 y30 i/o - w28 d28 aa32 i/o - y31 a27 aa31 i/o - y30 e29 aa30 i/o - y29 c27 ab32 gnd - gnd* gnd* gnd* i/o p38 y28 g25 aa29 i/o p39 aa30 d26 ab31 vcc p40 vcc* vcc* vcc* i/o p41 aa29 f26 ac31 i/o p42 ab31 b28 ab29 i/o p43 ab30 d30 ad32 i/o p44 ab29 a29 ac30 gnd p45 gnd* gnd* gnd* i/o - ab28 c29 ad31 i/o - ac30 g27 ae33 i/o p46 ac29 f30 ac29 i/o p47 ac28 b30 ae32 i/o - - e31 ad30 i/o - - c31 ae31 gnd - gnd* gnd* gnd* i/o - ad31 f28 ag33 i/o - ad30 d32 ah33 i/o p48 ad29 b32 ae29 i/o p49 ad28 g31 ag31 i/o p50 ae30 a33 af30 i/o p51 ae29 c33 ah32 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - af31 b34 aj32 i/o - ae28 a35 af29 i/o - af30 e33 ah31 i/o - af29 d34 ag30 i/o p52 ag31 d36 ak32 i/o p53 af28 b36 aj31 gnd - gnd* gnd* gnd* i/o - ag30 f34 ag29 i/o - ag29 d38 al33 i/o p54 ah31 c37 ah30 i/o p55 ag28 g37 ak31 i/o p56 ah30 b38 aj30 i/o, gck2 p57 aj30 f38 ah29 o (m1) p58 ah29 a39 ak30 gnd p59 gnd* gnd* gnd* i (m0) p60 ah28 e35 aj29 vcc p61 vcc* vcc* vcc* i (m2) p62 aj28 g33 an32 i/o, gck3 p63 ak29 j37 aj28 i/o (hdc) p64 ah27 g35 ak29 i/o p65 ak28 k36 al30 i/o p66 aj27 c39 ak28 i/o p67 al28 k38 am31 i/o (ldc) p68 ah26 c41 aj27 gnd - gnd* gnd* gnd* i/o - ak27 d40 an31 i/o - aj26 l37 al29 i/o - al27 h36 ak27 i/o - ah25 m36 al28 i/o - ak26 j35 aj26 i/o - al26 e41 am30 xc4062xl pad name hq240 bg432 pg475 bg560
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-147 xc4000e and xc4000x series field programmable gate arrays vcc - vcc* vcc* vcc* gnd - gnd* gnd* gnd* i/o p69 ah24 f40 am29 i/o p70 aj25 h38 ak26 i/o p71 ak25 n37 al27 i/o p72 aj24 l35 aj25 i/o - ah23 r35 an29 i/o - ak24 g41 an28 gnd - gnd* gnd* gnd* i/o - - h40 am26 i/o - - p38 ak24 i/o p73 al24 j39 al25 i/o p74 ah22 r37 aj23 i/o - aj23 j41 an26 i/o - ak23 k40 al24 gnd p75 gnd* gnd* gnd* i/o p76 aj22 l39 ak23 i/o p77 ak22 m38 an25 i/o p78 al22 t36 aj22 i/o p79 aj21 m40 al23 vcc p80 vcc* vcc* vcc* i/o p81 ah20 n39 am24 i/o p82 ak21 n41 ak22 gnd - gnd* gnd* gnd* i/o - aj20 p40 ak21 i/o - ah19 t38 am22 i/o - ak20 u35 aj20 i/o - aj19 u37 al21 i/o - al20 r39 an21 i/o - ah18 r41 ak20 gnd p83 gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - ak19 v36 al20 i//o - aj18 u39 aj19 i/o p84 al19 v38 am20 i/o p85 ak18 v40 ak19 i/o p86 ah17 w37 al19 i/o p87 aj17 w35 an19 gnd - gnd* gnd* gnd* i/o - - w41 aj18 i/o - - y36 ak18 i/o - ak17 w39 al18 i/o - al17 ab36 am18 i/o p88 aj16 y40 ak17 i/o ( init) p89 ak16 y38 aj17 vcc p90 vcc* vcc* vcc* gnd p91 gnd* gnd* gnd* i/o p92 al16 aa39 al17 i/o p93 ah15 ab38 am17 i/o - al15 ab40 an17 i/o - aj15 ac37 ak16 i/o - - ac39 aj16 i/o - - ac41 al16 gnd - gnd* gnd* gnd* i/o p94 ak15 ad36 am16 i/o p95 aj14 ac35 al15 i/o p96 ah14 ae37 ak15 i/o p97 ak14 ad40 aj15 i/o - al13 ad38 an15 i/o - ak13 ae39 am14 vcc - vcc* vcc* vcc* gnd p98 gnd* gnd* gnd* i/o - aj13 ag41 al14 i/o - ah13 ag39 ak14 i/o - al12 ag37 aj14 i/o - ak12 ae35 an13 i/o - aj12 ah38 am13 i/o - ak11 af38 al13 gnd - gnd* gnd* gnd* i/o p99 ah12 af36 ak12 xc4062xl pad name hq240 bg432 pg475 bg560 i/o p100 aj11 ah40 an11 vcc p101 vcc* vcc* vcc* i/o p102 al10 aj41 aj12 i/o p103 ak10 aj39 al11 i/o p104 aj10 aj37 ak11 i/o p105 ak9 ag35 am10 gnd p106 gnd* gnd* gnd* i/o - al8 ak40 al10 i/o - ah10 ak38 aj11 i/o p107 aj9 al37 an9 i/o p108 ak8 al39 ak10 i/o - - am38 am9 i/o - - am40 al9 gnd - gnd* gnd* gnd* i/o - aj8 an41 an7 i/o - ah9 am36 aj9 i/o p109 ak7 ak36 al7 i/o p110 al6 au41 ak8 i/o p111 aj7 an39 an6 i/o p112 ah8 ap40 am6 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - ak6 ar41 aj8 i/o - al5 al35 al6 i/o p113 ah7 av40 ak7 i/o p114 aj6 an37 am5 i/o - ak5 at38 am4 i/o - al4 ap38 aj7 gnd - gnd* gnd* gnd* i/o - ah6 at40 al5 i/o - aj5 aw39 ak6 i/o p115 ak4 ap36 an3 i/o p116 ah5 au37 ak5 i/o p117 ak3 ar37 aj6 i/o, gck4 p118 aj4 au39 al4 gnd p119 gnd* gnd* gnd* done p120 ah4 ar35 aj5 vcc p121 vcc* vcc* vcc* program p122 ah3 an35 am1 i/o (d7) p123 aj2 au35 ah5 i/o, gck5 p124 ag4 av38 aj4 i/o p125 ag3 at34 ak3 i/o p126 ah2 ba39 ah4 i/o - ah1 au33 al1 i/o - af4 ay38 ag5 gnd - gnd* gnd* gnd* i/o p127 af3 av36 aj3 i/o p128 ag2 ar31 ak2 i/o - ag1 ar33 ag4 i/o - ae4 av32 ah3 i/o - ae3 ba37 af5 i/o - af2 ay36 aj2 vcc - vcc* vcc* vcc* gnd - gnd* gnd* gnd* i/o (d6) p129 af1 av34 aj1 i/o p130 ad4 ba35 af4 i/o p131 ad3 au31 ag3 i/o p132 ae2 ay34 ae5 i/o - ad2 at30 ah1 i/o - ac4 aw33 af3 gnd - gnd* gnd* gnd* i/o - - ba33 af1 i/o - - av30 ad4 i/o p133 ac3 ay32 ae3 i/o p134 ad1 au29 ac5 i/o - ac2 aw31 ae1 i/o - ab4 ba31 ad3 gnd p135 gnd* gnd* gnd* i/o p136 ab3 ar27 ac4 i/o p137 ab2 at28 ad2 xc4062xl pad name hq240 bg432 pg475 bg560
r xc4000e and xc4000x series field programmable gate arrays 6-148 ds006 (v. 1.7) october 4, 1999 - product speci?cation i/o p138 ab1 ay30 ab5 i/o p139 aa3 aw29 ac3 vcc p140 vcc* vcc* vcc* i/o (d5) p141 aa2 ba29 aa5 i/o (cs0) p142 y2 ay28 ab3 gnd p143 gnd* gnd* gnd* i/o - y4 ar25 ab2 i/o - y3 av28 aa4 i/o - y1 aw27 aa3 i/o - w1 at26 y5 i/o - w4 av26 y3 i/o - w3 ba27 y2 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o - w2 aw25 w5 i/o - v2 av24 w4 i/o - v4 au25 w3 i/o - v3 ar23 w1 i/o p144 u1 at24 v3 i/o p145 u2 ay24 v5 gnd - gnd* gnd* gnd* i/o p146 u4 ba23 v4 i/o p147 u3 au23 v2 i/o - - aw23 u2 i/o - - av20 u1 i/o (d4) p148 t1 ay22 u5 i/o p149 t2 av22 u4 vcc p150 vcc* vcc* vcc* gnd p151 gnd* gnd* gnd* i/o (d3) p152 t3 aw21 u3 i/o ( rs) p153 r1 ba21 t2 i/o - - au19 t3 i/o - - ay20 t5 i/o p154 r2 au17 t4 i/o p155 r4 aw19 r1 gnd - gnd* gnd* gnd* i/o p156 r3 ba19 r3 i/o p157 p2 at16 r4 i/o - p3 ar19 r5 i/o - p4 av14 p2 i/o - n1 ay18 p3 i/o - n2 av18 p4 vcc - vcc* vcc* vcc* gnd p158 gnd* gnd* gnd* i/o - n3 at18 n1 i/o - n4 aw17 p5 i/o - m1 ar15 n2 i/o - m2 ba15 n3 i/o - m3 at14 n5 i/o - m4 ar17 m3 gnd - gnd* gnd* gnd* i/o (d2) p159 l2 aw15 m4 i/o p160 l3 av16 l1 vcc p161 vcc* vcc* vcc* i/o p162 k1 ay14 k2 i/o p163 k2 ba13 l4 i/o p164 k3 au13 j1 i/o p165 k4 aw13 k3 gnd p166 gnd* gnd* gnd* i/o - j2 ay12 l5 i/o - j3 ba11 j2 i/o p167 j4 av12 k4 i/o p168 h1 at12 j3 i/o - - aw11 h2 i/o - - ay10 k5 gnd - gnd* gnd* gnd* i/o p169 h2 ba9 g1 i/o p170 h3 au11 f1 i/o p171 h4 aw9 j5 i/o p172 g2 av10 g3 xc4062xl pad name hq240 bg432 pg475 bg560 i/o - g3 ay8 h4 i/o - f1 ba7 f2 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o (d1) p173 g4 av8 f3 i/o (rclk, rdy/busy) p174 f2 ay6 g4 i/o - f3 ar11 d2 i/o - e1 at8 e3 i/o - f4 au9 g5 i/o - e2 aw5 c1 gnd - gnd* gnd* gnd* i/o - e3 ay4 f4 i/o - d1 ba5 d3 i/o p175 e4 av4 b3 i/o p176 d2 ar9 f5 i/o (d0, din) p177 c2 au5 e4 i/o, gck6 (dout) p178 d3 av6 d4 cclk p179 d4 ar5 c4 vcc p180 vcc* vcc* vcc* o, tdo p181 c4 an7 e6 gnd p182 gnd* gnd* gnd* i/o (a0, ws) p183 b3 ar7 d5 i/o, gck7 (a1) p184 d5 aw3 a2 i/o p185 b4 au3 d6 i/o p186 c5 aw1 a3 i/o - a4 ap6 e7 i/o - d6 av2 c5 gnd - gnd* gnd* gnd* i/o - b5 at4 b4 i/o - c6 an5 d7 i/o (cs1, a2) p187 a5 au1 c6 i/o (a3) p188 d7 am6 e8 i/o - b6 at2 b5 i/o - a6 al7 a5 vcc - vcc* vcc* vcc* gnd - gnd* gnd* gnd* i/o p189 d8 ar1 d8 i/o p190 c7 ap2 c7 i/o p191 b7 am4 e9 i/o p192 d9 an3 a6 i/o - b8 al5 b7 i/o - a8 ak6 d9 gnd - gnd* gnd* gnd* i/o - - an1 d10 i/o - - aj5 c9 i/o p193 d10 am2 e11 i/o p194 c9 ah4 a9 i/o p195 b9 al3 c10 i/o - c10 ak4 d11 gnd p196 gnd* gnd* gnd* i/o p197 b10 ag7 b10 i/o p198 a10 ag5 e12 i/o p199 c11 ak2 c11 i/o p200 d12 aj3 b11 vcc p201 vcc* vcc* vcc* i/o - b11 aj1 d12 i/o - c12 af6 a11 gnd - gnd* gnd* gnd* i/o - d13 ah2 c13 i/o - b12 af4 e14 i/o - c13 ae7 a13 i/o - a12 ae5 d14 i/o - d14 ag3 c14 i/o - b13 ag1 b14 gnd - gnd* gnd* gnd* vcc - vcc* vcc* vcc* i/o (a4) p202 c14 ad6 e15 i/o (a5) p203 a13 ad4 d15 i/o p205 b14 ae3 c15 i/o p206 d15 ac5 a15 xc4062xl pad name hq240 bg432 pg475 bg560
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-149 xc4000e and xc4000x series field programmable gate arrays * pads labelled gnd* or vcc* are internally bonded to ground or vcc planes within the package. they have no direct connection to any specific package pin. additional xc4062xl package pins note: these pins may be not connected for this device revision, however for compatability with other devices in this package, these pins should be tied to gnd. xc4085xl device pinout tables i/o (a21) p207 c15 ad2 c16 i/o (a20) p208 b15 ac7 e16 gnd - gnd* gnd* gnd* i/o - - ac1 d16 i/o - - ac3 b16 i/o - a15 ab6 b17 i/o - c16 ab2 c17 i/o (a6) p209 b16 ab4 e17 i/o (a7) p210 a16 aa3 d17 gnd p211 gnd* gnd* gnd* 6/16/97 hq240 gnd pins p204 p219 ---- 5/5/97 bg432 vcc pins a1 a11 a21 a31 c3 c29 d11 d21 l1 l4 l28 l31 aa1 aa4 aa28 aa31 ah11 ah21 aj3 aj29 al1 al11 al21 al31 - - - - gnd pins a2 a3 a7 a9 a14 a18 a23 a25 a29 a30 b1 b2 b30 b31 c1 c31 d16 g1 g31 j1 j31 p1 p31 t4 t28 v1 v31 ac1 ac31 ae1 ae31 ah16 aj1 aj31 ak1 ak2 ak30 ak31 al2 al3 al7 al9 al14 al18 al23 al25 al29 al30 - not connected pins c8------ 5/5/97 xc4062xl pad name hq240 bg432 pg475 bg560 pg475 vcc pins a37 b2 b16 b26 b40 d2 e21 f6 f36 g13 g29 n7 n35 t2 t40 aa1 aa5 aa37 aa41 af2 af40 aj7 aj35 ar13 ar29 at6 at22 at36 au21 aw37 aw41 ay2 ay16 ay26 ay40 ba3 gnd pins a3 c1 c7 g3 l1 p6 u1 a17 a25 a41 aa7 ae1 ah6 al1 ar3 aw7 ba1 c35 e15 e27 f10 f32 g21 g39 l41 p36 u41 aa35 ae41 ah36 al41 ar21 ar39 at10 at20 at32 au15 au27 aw35 ba17 ba25 ba41 e37 e39 a31 j7 ap4 au7 5/5/97 bg560 vcc pins a4 a10 a16 a22 a26 a30 b2 b13 b19 b32 c3 c31 c32 d1 d33 e5 h1 k33 m1 n32 r2 t33 v1 w32 aa2 ab33 ad1 af33 ak1 ak4 ak33 al2 al3 al31 am2 am15 am21 am32 an4 an8 an12 an18 an24 an30 ----- gnd pins a7 a12 a14 a18 a20 a24 a29 a32 b1 b6 b9 b15 b23 b27 b31 c2 e1 f32 g2 g33 j32 k1 l2 m33 p1 p33 r32 t1 v33 w2 y1 y33 ab1 ac32 ad33 ae2 ag1 ag32 ah2 aj33 al32 am3 am11 am19 am25 am28 am33 am7 an2 an5 an10 an14 an16 an20 an22 an27 not connected pins a1 a8 a23 a27 a28 a33 b8 b12 c8 c12 c22 c26 d13 d22 d25 e2 e10 e13 e21 e32 e33 h3 h5 h31 j4 k29 l3 l31 m2 m5 m30 n4 n30 n31 y4 y29 aa1 aa33 ab4 ab30 ac1 ac2 ac33 ad5 ad29 ae4 ae30 af2 af31 af32 ag2 aj10 aj13 aj21 aj24 ak9 ak13 ak25 al8 al12 al22 al26 am8 am12 am23 am27 an1 an23 an33 - 5/5/97 xc4085xl pad name bg432 bg560 pg559 vcc vcc vcc* vcc* i/o (a8) d17 a17 ab6 i/o (a9) a17 b18 ab4 i/o c17 c18 aa7 i/o b17 e18 ac1 i/o - d18 aa5 i/o - a19 aa3 gnd gnd* gnd* gnd* i/o (a19) c18 c19 y8 i/o (a18) d18 d19 ab2 i/o b18 e19 y6 i/o a19 b20 aa1 i/o (a10) b19 c20 y4 i/o (a11) c19 d20 w7 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o d19 a21 w5 i/o a20 e20 v6 i/o b20 b21 v4 i/o c20 c21 y2 i/o b21 d21 u3 i/o d20 b22 u7 i/o - e21 v2 i/o - c22 u5 gnd gnd* gnd* gnd* i/o - d22 t4 xc4085xl pad name bg432 bg560 pg559
r xc4000e and xc4000x series field programmable gate arrays 6-150 ds006 (v. 1.7) october 4, 1999 - product speci?cation i/o - a23 u1 i/o c21 c23 r3 i/o a22 e22 r5 vcc vcc vcc* vcc* i/o b22 b24 t8 i/o c22 d23 t2 i/o b23 c24 p4 i/o a24 a25 r7 gnd gnd* gnd* gnd* i/o d22 e23 n3 i/o c23 b25 r1 i/o b24 d24 n5 i/o c24 c25 p2 i/o - b26 m4 i/o - e24 l1 i/o - c26 l3 i/o - d25 p8 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o - a27 n7 i/o - a28 k2 i/o d23 e25 m6 i/o b25 c27 j1 i/o a26 d26 l5 i/o c25 b28 h2 i/o (a12) d24 b29 k4 i/o (a13) b26 e26 j3 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o a27 c28 l7 i/o d25 d27 j5 i/o c26 b30 g1 i/o b27 c29 h4 i/o a28 e27 f2 i/o d26 a31 g5 gnd gnd* gnd* gnd* i/o c27 d28 h6 i/o b28 c30 k8 i/o d27 d29 d2 i/o b29 e28 j7 i/o (a14) c28 d30 f4 i/o, gck8 (a15) d28 e29 e3 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o, gck1 (a16) d29 b33 c1 i/o (a17) c30 f29 c3 i/o e28 e30 f6 i/o e29 d31 a3 i/o (tdi) d30 f30 h8 i/o (tck) d31 c33 d4 gnd gnd* gnd* gnd* i/o f28 g29 d6 i/o f29 e31 c5 i/o e30 d32 e7 i/o e31 g30 b4 i/o g28 f31 h10 i/o g29 h29 g9 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o - e32 f8 xc4085xl pad name bg432 bg560 pg559 i/o - e33 d8 i/o f30 h30 b6 i/o f31 g31 e9 i/o h28 j29 a7 i/o h29 f33 g11 i/o g30 g32 h14 i/o h30 j30 f12 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o - h31 g13 i/o - k29 e11 i/o - h32 b8 i/o - j31 d10 i/o j28 k30 a9 i/o j29 h33 g15 i/o h31 l29 b10 i/o j30 k31 h16 gnd gnd* gnd* gnd* i/o k28 l30 c9 i/o k29 k32 e13 i/o (tms) k30 j33 a11 i/o k31 m29 d12 vcc vcc* vcc* vcc* i/o - l31 c11 i/o - m30 b14 i/o l29 l32 g17 i/o l30 m31 e15 gnd gnd* gnd* gnd* i/o m30 n29 d14 i/o m28 l33 a15 i/o - n30 c13 i/o - n31 b16 i/o m29 m32 e17 i/o m31 p29 f18 i/o n31 p30 a17 i/o n28 n33 g19 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o n29 p31 d16 i/o n30 p32 c15 i/o p30 r29 b18 i/o p28 r30 h20 i/o p29 r31 b20 i/o r31 r33 e19 gnd gnd* gnd* gnd* i/o r30 t31 d18 i/o r28 t29 f20 i/o - t30 g21 i/o - t32 c17 i/o r29 u32 d20 i/o t31 u31 e21 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o t30 u29 c21 i/o t29 u30 f22 i/o - u33 a21 i/o - v32 d22 i/o u31 v31 b22 i/o u30 v29 g23 gnd gnd* gnd* gnd* i/o u28 v30 e23 xc4085xl pad name bg432 bg560 pg559
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-151 xc4000e and xc4000x series field programmable gate arrays i/o u29 w33 c23 i/o v30 w31 a23 i/o v29 w30 d24 i/o v28 w29 b24 i/o w31 y32 h24 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o w30 y31 f24 i/o w29 y30 e25 i/o - aa33 b26 i/o - y29 d26 i/o w28 aa32 a27 i/o y31 aa31 g25 i/o y30 aa30 b28 i/o y29 ab32 c27 gnd gnd* gnd* gnd* i/o y28 aa29 f26 i/o aa30 ab31 e27 i/o - ab30 a29 i/o - ac33 d28 vcc vcc* vcc* vcc* i/o aa29 ac31 g27 i/o ab31 ab29 b30 i/o ab30 ad32 c29 i/o ab29 ac30 e29 gnd gnd* gnd* gnd* i/o ab28 ad31 d30 i/o ac30 ae33 a33 i/o ac29 ac29 c31 i/o ac28 ae32 b34 i/o - ad30 h28 i/o - ae31 a35 i/o - af32 g29 i/o - ad29 e31 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o - af31 d32 i/o - ae30 c35 i/o ad31 ag33 c33 i/o ad30 ah33 b36 i/o ad29 ae29 h30 i/o ad28 ag31 a37 i/o ae30 af30 g31 i/o ae29 ah32 f32 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o af31 aj32 e33 i/o ae28 af29 d34 i/o af30 ah31 b38 i/o af29 ag30 g33 i/o ag31 ak32 a41 i/o af28 aj31 e35 gnd gnd* gnd* gnd* i/o ag30 ag29 d36 i/o ag29 al33 f36 i/o ah31 ah30 g35 i/o ag28 ak31 h34 i/o ah30 aj30 b40 i/o, gck2 aj30 ah29 e37 o (m1) ah29 ak30 d38 gnd gnd* gnd* gnd* xc4085xl pad name bg432 bg560 pg559 i (m0) ah28 aj29 c39 vcc vcc* vcc* vcc* i (m2) aj28 an32 h36 i/o, gck3 ak29 aj28 f38 i/o (hdc) ah27 ak29 c41 i/o ak28 al30 d40 i/o aj27 ak28 b42 i/o al28 am31 j37 i/o ( ldc) ah26 aj27 k36 gnd gnd* gnd* gnd* i/o ak27 an31 h38 i/o aj26 al29 d42 i/o al27 ak27 g39 i/o ah25 al28 c43 i/o ak26 aj26 f40 i/o al26 am30 e41 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o ah24 am29 l37 i/o aj25 ak26 j39 i/o ak25 al27 f42 i/o aj24 aj25 h40 i/o ah23 an29 g43 i/o ak24 an28 j41 i/o - ak25 h42 i/o - al26 n37 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o - aj24 p36 i/o - am27 m38 i/o - am26 j43 i/o - ak24 l39 i/o al24 al25 k42 i/o ah22 aj23 k40 i/o aj23 an26 l43 i/o ak23 al24 l41 gnd gnd* gnd* gnd* i/o aj22 ak23 r37 i/o ak22 an25 p42 i/o al22 aj22 t36 i/o aj21 al23 n39 vcc vcc* vcc* vcc* i/o ah20 am24 m40 i/o ak21 ak22 r43 i/o - am23 n41 i/o - aj21 r39 gnd gnd* gnd* gnd* i/o - al22 u37 i/o - an23 t42 i/o aj20 ak21 p40 i/o ah19 am22 u43 i/o ak20 aj20 r41 i/o aj19 al21 v42 i/o al20 an21 u39 i/o ah18 ak20 v38 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o ak19 al20 w37 i/o aj18 aj19 t40 i/o al19 am20 y42 i/o ak18 ak19 u41 xc4085xl pad name bg432 bg560 pg559
r xc4000e and xc4000x series field programmable gate arrays 6-152 ds006 (v. 1.7) october 4, 1999 - product speci?cation i/o ah17 al19 y36 i/o aj17 an19 v40 gnd gnd* gnd* gnd* i/o - aj18 w39 i/o - ak18 aa43 i/o ak17 al18 y38 i/o al17 am18 y40 i/o aj16 ak17 aa37 i/o ( init) ak16 aj17 aa39 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o al16 al17 aa41 i/o ah15 am17 ab38 i/o al15 an17 ab42 i/o aj15 ak16 ab40 i/o - aj16 ac37 i/o - al16 ac39 gnd gnd* gnd* gnd* i/o ak15 am16 ad36 i/o aj14 al15 ac41 i/o ah14 ak15 ad38 i/o ak14 aj15 ac43 i/o al13 an15 ad40 i/o ak13 am14 ae39 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o aj13 al14 ae37 i/o ah13 ak14 af40 i/o al12 aj14 ad42 i/o ak12 an13 af42 i/o aj12 am13 af38 i/o ak11 al13 ag39 i/o - ak13 ag43 i/o - aj13 ag37 gnd gnd* gnd* gnd* i/o - am12 ah40 i/o - al12 aj41 i/o ah12 ak12 ag41 i/o aj11 an11 ak40 vcc vcc* vcc* vcc* i/o al10 aj12 aj39 i/o ak10 al11 ah42 i/o aj10 ak11 ah36 i/o ak9 am10 al39 gnd gnd* gnd* gnd* i/o al8 al10 aj37 i/o ah10 aj11 aj43 i/o aj9 an9 am40 i/o ak8 ak10 ak42 i/o - am9 an41 i/o - al9 al41 i/o - aj10 ar41 i/o - am8 ak36 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o - ak9 al37 i/o - al8 an43 i/o aj8 an7 am38 i/o ah9 aj9 ap42 i/o ak7 al7 an39 i/o al6 ak8 ar43 xc4085xl pad name bg432 bg560 pg559 i/o aj7 an6 ap40 i/o ah8 am6 at40 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o ak6 aj8 an37 i.o al5 al6 ar39 i/o ah7 ak7 at42 i/o aj6 am5 ba43 i/o ak5 am4 au43 i/o al4 aj7 au39 gnd gnd* gnd* gnd* i/o ah6 al5 at38 i/o aj5 ak6 ap36 i/o ak4 an3 ar37 i/o ah5 ak5 av42 i/o ak3 aj6 av40 i/o, gck4 aj4 al4 aw41 gnd gnd* gnd* gnd* done ah4 aj5 ay42 vcc vcc* vcc* vcc* program ah3 am1 bb42 i/o (d7) aj2 ah5 bc41 i/o, gck5 ag4 aj4 av38 i/o ag3 ak3 ba39 i/o ah2 ah4 at36 i/o ah1 al1 bb40 i/o af4 ag5 ay40 gnd gnd* gnd* gnd* i/o af3 aj3 ba41 i/o ag2 ak2 bb38 i/o ag1 ag4 ay38 i/o ae4 ah3 bc37 i/o ae3 af5 aw37 i/o af2 aj2 at34 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o (d6) af1 aj1 au35 i/o ad4 af4 av36 i/o ad3 ag3 bb36 i/o ae2 ae5 ay36 i/o ad2 ah1 bc35 i/o ac4 af3 aw35 i/o - ae4 au33 i/o - ag2 at30 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o - ad5 av32 i/o - af2 au31 i/o - af1 aw33 i/o - ad4 bb34 i/o ac3 ae3 ay34 i/o ad1 ac5 bc33 i/o ac2 ae1 au29 i/o ab4 ad3 at28 gnd gnd* gnd* gnd* i/o ab3 ac4 ba35 i/o ab2 ad2 bb30 i/o ab1 ab5 aw31 i/o aa3 ac3 ay32 vcc vcc* vcc* vcc* i/o - ab4 ba33 xc4085xl pad name bg432 bg560 pg559
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-153 xc4000e and xc4000x series field programmable gate arrays i/o - ac1 au27 i/o (d5) aa2 aa5 bc29 i/o ( cs0) y2 ab3 aw29 gnd gnd* gnd* gnd* i/o y4 ab2 ay30 i/o y3 aa4 ba31 i/o y1 aa3 bb28 i/o w1 y5 aw27 i/o - aa1 bc27 i/o - y4 av26 i/o w4 y3 au25 i/o w3 y2 ay28 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o w2 w5 ba29 i/o v2 w4 at24 i/o v4 w3 bb26 i/o v3 w1 aw25 i/o u1 v3 bb24 i/o u2 v5 ay26 gnd gnd* gnd* gnd* i/o u4 v4 av24 i/o u3 v2 au23 i/o - u2 ba27 i/o - u1 bc23 i/o (d4) t1 u5 ay24 i/o t2 u4 aw23 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o (d3) t3 u3 ba23 i/o ( rs) r1 t2 av22 i/o - t3 ay22 i/o - t5 bb22 i/o r2 t4 au21 i/o r4 r1 aw21 gnd gnd* gnd* gnd* i/o r3 r3 ba21 i/o p2 r4 bc21 i/o p3 r5 ay20 i/o p4 p2 bb20 i/o n1 p3 at20 i/o n2 p4 av20 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o n3 n1 aw19 i/o n4 p5 ay18 i/o m1 n2 bb18 i/o m2 n3 au19 i/o - n4 bc17 i/o - m2 ba17 i/o m3 n5 av18 i/o m4 m3 aw17 gnd gnd* gnd* gnd* i/o (d2) l2 m4 ay16 i/o l3 l1 bb16 i/o - l3 au17 i/o - m5 ba15 vcc vcc* vcc* vcc* i/o k1 k2 aw15 i/o k2 l4 bc15 i/o k3 j1 ay14 xc4085xl pad name bg432 bg560 pg559 i/o k4 k3 ba13 gnd gnd* gnd* gnd* i/o j2 l5 at16 i/o j3 j2 bb14 i/o j4 k4 au15 i/o h1 j3 bc11 i/o - h2 aw13 i/o - k5 bb10 i/o - h3 ay12 i/o - j4 ba11 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o h2 g1 at14 i/o h3 f1 au13 i/o h4 j5 av12 i/o g2 g3 bc9 i/o g3 h4 aw11 i/o f1 f2 bb8 i/o - e2 ay10 i/o - h5 au11 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o (d1) g4 f3 ba9 i/o ( rclk rdy/ busy) f2 g4 aw9 i/o f3 d2 bc7 i/o e1 e3 ay8 i/o f4 g5 av8 i/o e2 c1 at10 gnd gnd* gnd* gnd* i/o e3 f4 au9 i/o d1 d3 bb6 i/o e4 b3 aw7 i/o d2 f5 bc3 i/o (d0, din) c2 e4 ay6 i/o, gck6 (dout) d3 d4 bb4 cclk d4 c4 ba5 vcc vcc* vcc* vcc* o, tdo c4 e6 ba3 gnd gnd* gnd* gnd* i/o (a0, ws) b3 d5 at8 i/o, gck7 (a1) d5 a2 av6 i/o b4 d6 bb2 i/o c5 a3 ay4 i/o a4 e7 ar7 i/o d6 c5 ap8 gnd gnd* gnd* gnd* i/o b5 b4 at6 i/o c6 d7 ay2 i/o (cs1, a2) a5 c6 au5 i/o (a3) d7 e8 ba1 i/o b6 b5 av4 i/o a6 a5 aw3 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o d8 d8 an7 i/o c7 c7 ar5 i/o b7 e9 av2 i/o d9 a6 at4 i/o b8 b7 au1 i/o a8 d9 ar3 xc4085xl pad name bg432 bg560 pg559
r xc4000e and xc4000x series field programmable gate arrays 6-154 ds006 (v. 1.7) october 4, 1999 - product speci?cation *pads labelled gnd* or vcc* are internally bonded to ground or vcc planes within the package. they have no direct connection to any specific package pin. additional xc4085xl package pins i/o - c8 at2 i/o - e10 al7 vcc vcc* vcc* vcc* gnd gnd* gnd* gnd* i/o - b8 ak8 i/o - a8 am6 i/o - d10 an5 i/o - c9 ar1 i/o d10 e11 ap4 i/o c9 a9 an3 i/o b9 c10 ap2 i/o c10 d11 aj7 gnd gnd* gnd* gnd* i/o b10 b10 ah8 i/o a10 e12 al5 i/o c11 c11 an1 i/o d12 b11 am4 vcc vcc* vcc* vcc* i/o b11 d12 al3 i/o c12 a11 aj5 i/o - e13 ak2 i/o - c12 ag7 gnd gnd* gnd* gnd* i/o - b12 ak4 i/o - d13 aj3 i/o d13 c13 ag5 i/o b12 e14 aj1 i/o c13 a13 af6 i/o a12 d14 ah2 i/o d14 c14 ae7 i/o b13 b14 ah4 gnd gnd* gnd* gnd* vcc vcc* vcc* vcc* i/o (a4) c14 e15 ag3 i/o (a5) a13 d15 ad8 i/o b14 c15 ag1 i/o d15 a15 af4 i/o (a21) c15 c16 ae5 i/o (a20) b15 e16 ad6 gnd gnd* gnd* gnd* i/o - d16 ad4 i/o - b16 af2 i/o a15 b17 ac7 i/o c16 c17 ad2 i/o (a6) b16 e17 ac5 i/o (a7) a16 d17 ac3 gnd gnd* gnd* gnd* 6/13/97 xc4085xl pad name bg432 bg560 pg559 bg560 vcc pins a4 a10 a16 a22 a26 a30 b2 b13 b19 b32 c3 c31 c32 d1 d33 e5 h1 k33 m1 n32 r2 t33 v1 w32 aa2 ab33 ad1 af33 ak1 ak4 ak33 al2 al3 al31 am2 am15 am21 am32 an4 an8 an12 an18 an24 an30 - - - - - gnd pins a7 a12 a14 a18 a20 a24 a29 a32 b1 b6 b9 b15 b23 b27 b31 c2 e1 f32 g2 g33 j32 k1 l2 m33 p1 p33 r32 t1 v33 w2 y1 y33 ab1 ac32 ad33 ae2 ag1 ag32 ah2 aj33 al32 am3 am11 am19 am25 am28 am33 am7 an2 an5 an10 an14 an16 an20 an22 an27 not connected pins a1 a33 ac2 an1 an33 - - 6/4/97 pg559 vcc pins a13 a31 a43 b2 c7 c19 c25 c37 f14 f30 g3 g7 g37 g41 h12 h18 h26 h32 m8 m36 n1 n43 p6 p38 v8 v36 w3 w41 ae3 ae41 af8 af36 ak6 ak38 al1 al43 am8 am36 at12 at18 at26 at32 au3 au7 au37 au41 av14 av30 ba7 ba19 ba25 ba37 bc1 bc13 bc31 bc43 gnd pins a5 a19 a25 a39 b12 b32 e1 e5 e39 e43 f10 f16 f28 f34 h22 k6 k38 m2 m42 t6 t38 w1 w43 ab8 ab36 ae1 ae43 ah6 ah38 am2 am42 ap6 ap38 at22 av10 av16 av28 av34 aw1 aw5 aw39 aw43 bb12 bb32 bc5 bc19 bc25 bc39 - 5/8/97
r ds006 (v. 1.7) october 4, 1999 - product speci?cation 6-155 xc4000e and xc4000x series field programmable gate arrays vg432 vcc pins a1 a11 a21 a31 d11 d21 l1 l4 l28 l31 aa1 aa4 aa28 aa31 ah11 ah21 al1 al11 al21 al31 c3 c29 aj3 aj29 gnd pins a2 a3 a7 a9 a14 a18 a23 a25 a29 a30 b1 b2 b30 b31 c1 c31 d16 g1 g31 j1 j31 p1 p31 t4 t28 v1 v31 ac1 ac31 ae1 ae31 ah16 aj1 aj31 ak1 ak2 ak30 ak31 al2 al3 al7 al9 al14 al18 al23 al25 al29 al30 not connected pins c8 3/3/98
r xc4000e and xc4000x series field programmable gate arrays 6-156 ds006 (v. 1.7) october 4, 1999 - product speci?cation revision control version description 3/30/98 (1.5) added xc4002xl 1/29/99 (1.5) updated pin diagrams 5/14/99 (1.6) replaced electrical specification and pinout pages for e, ex, and xl families with separate updates and added url link on placeholder page for electrical specifications/pinouts for weblinx users 10/4/99 (1.7) added note about extra grounds in center of bg256 package for xc4028xl (page 6-133).

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